Abstract: A method for manufacturing a semiconductor device is provided. The method includes disposing a mandrel layer on a dielectric layer and patterning the mandrel layer to form a first mandrel and a second mandrel spaced apart from the first mandrel. The minimum distance between the first mandrel and the second mandrel is equal to or less than about 90 nm. The method also includes etching the dielectric layer by using the first spacer, the second spacer, the third spacer, and the fourth spacer as etching masks to form a first dielectric element, a second dielectric element, a third dielectric element, and a fourth dielectric element. The method also includes forming a first shielding line between the second dielectric element and the third dielectric element.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a surface, a first signal line disposed on the surface of the substrate, and a second signal line disposed on the surface of the substrate and spaced apart from the first signal line. The semiconductor device also includes a first shielding line between the first signal line and the second signal line. The minimum distance between the first signal line and the second signal line is equal to or less than about 90 nanometers (nm).

Abstract: A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin, the gate structure comprising: a first metallic layer; a second metallic layer over the first metallic layer, wherein the first metallic layer is a metal compound of a first element and a second element and the second metallic layer is a single-element metal of the second element; and an oxide layer between the first metallic layer and the second metallic layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.

Abstract: In a method of manufacturing a semiconductor device, an initial pattern layout is obtained. The initial pattern layout incudes fin patterns which include active fin patterns to be formed as active fin structures and dummy fin patterns not to be formed as actual fin structures or to be removed. The locations of the fin patterns are modified, as follows. A space between adjacent active fin patterns is increased by a first amount, a space between the dummy fin patterns is decreased by a second amount, and a space between one of the dummy fin patterns and one of the active fin patterns adjacent to the one of the dummy fin patterns is decreased by a third amount. Mandrel patterns are placed so that the fin patterns of which locations are modified are placed along longitudinal edges of the mandrel patterns.

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a first electrode layer formed over a substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure also includes a first dielectric layer formed on the first spacers, and an end of the first dielectric layer is in direct contact with the first pacer.

Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data sate. The first random bit is then read from the MRAM cell.

Abstract: In some examples of the present disclosure, a non-transitory memory resource storing machine-readable instructions can cause a processing resource of a computing device to: instruct a first microphone of the computing device and a second microphone of a peripheral device to capture an audio signal generated by an audio source, determine a location of the second microphone based on a proximity of the peripheral device to the audio source, and alter a sound property of the audio signal based on a location of the first microphone and the location of the second microphone.

Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

Abstract: A processing chamber includes a grid and a first disk. The grid includes a plurality of holes arranged in the processing chamber. The grid partitions the processing chamber into a first chamber in which plasma is generated and a second chamber in which a pedestal is configured to support a substrate. The first disk is arranged in the second chamber. The first disk is movable between the grid and the substrate when supported on the pedestal.

Abstract: A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.

Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.

Abstract: A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.

Abstract: An array antenna includes a flexible substrate formed by stacked liquid crystal polymer (LCP) layers and has at least one feed point. At least one serial antenna is arranged on the flexible substrate, and a microstrip is extended from the feed point to connect a plurality of radiating elements in series to form the serial antenna. The tail end one of the radiating elements of the serial antenna is connected to one end of a ground microstrip, and another end of the ground microstrip is short-circuited to the ground. The length of the ground microstrip is approximately one fourth of the wavelength of the center frequency of the array antenna. Feeding sections where microstrips feeding to the radiating elements are in a horn and/or groove shape. Desired frequency and bandwidth may be obtained by adjusting lengths and widths of feeding sections respectively.

Abstract: Semiconductor devices including continuous-core connectors and associated systems and methods are disclosed herein. The continuous-core connectors each include a peripheral wall that surrounds an inner-core configured to provide an electrical path using uniform material.

Abstract: An electronic device including a chassis, a motherboard, an expansion card and a support. The motherboard is disposed in the chassis. The expansion card includes a circuit board assembly and a fixing plate. The circuit board assembly is fixed to a side of the fixing plate. The circuit board assembly is electrically connected to the motherboard and is fixed to the chassis via the fixing plate. A side of the support supports a side of the circuit board assembly that is located farthest from the fixing plate. A side of the support that is located farthest from the circuit board assembly is fixed to the motherboard and the chassis.

Abstract: An optical device is provided. The optical device includes a fiber array and an optical assembly. The fiber array includes a common channel and a plurality of divided. channels arranged in parallel in a first direction and extending along a second direction, and the fiber array has a first surface from a top view perspective. The optical assembly is coupled to the first surface of the fiber array. The first surface and the common channel of the fiber array form an angle less than 90 degrees from the top view perspective.

Abstract: A bidirectional electrostatic discharge protection device includes a first transient voltage suppressor chip, a second transient voltage suppressor chip, a first conductive wire, and a second conductive wire. The first transient voltage suppressor chip includes a first diode and a first bipolar junction transistor. The first diode and the first bipolar junction transistor are electrically connected to a first pin. The second transient voltage suppressor chip includes a second diode and a second bipolar junction transistor. The second diode and the second bipolar junction transistor are electrically connected to a second pin. The first conductive wire is electrically connected between the first diode and the second bipolar junction transistor. The second conductive wire is electrically connected between the second diode and the first bipolar junction transistor.

Abstract: A semiconductor package includes a substrate, a semiconductor die mounted on the substrate, and a heatsink over the semiconductor die. The heatsink includes a roof portion and at least one connecting portion extending between the roof portion and the substrate. The at least one connecting portion includes a connection lead mounted on a connection pad of the substrate. The connection pad includes a first portion and a second portion spaced apart from each other, which are configured to electrically couple to different voltage signals, respectively, for detecting heatsink floating.