Abstract: A charge pump circuit includes a power switch, a first pull-low circuit, an output pull-low circuit, a first charge pump stage and an output charge pump stage. The power switch receives an enabling signal. The first pull-low circuit and the output pull-low circuit receive a pull-low signal. The first charge pump stage includes a first boost capacitor used to receive a first phase signal, a first transfer transistor, a first gate-control transistor and a first storage capacitor used to receive a second phase signal. The output charge pump stage includes an output boost capacitor used to receive a third phase signal, an output transfer transistor and an output gate-control transistor. The charge pump circuit generates voltages in an erasing operation, a program operation and a read operation according to the enabling signal, the pull-low signal, the first phase signal, the second phase signal and the third phase signal.

Abstract: An electronic device including a chassis, a motherboard, an expansion card and a support. The motherboard is disposed in the chassis. The expansion card includes a circuit board assembly and a fixing plate. The circuit board assembly is fixed to a side of the fixing plate. The circuit board assembly is electrically connected to the motherboard and is fixed to the chassis via the fixing plate. A side of the support supports a side of the circuit board assembly that is located farthest from the fixing plate. A side of the support that is located farthest from the circuit board assembly is fixed to the motherboard and the chassis.

Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

Abstract: Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.

Abstract: A semiconductor device includes a substrate comprising a semiconductor fin, a gate structure over the semiconductor fin, and source/drain structures over the semiconductor fin and on opposite sides of the gate structure. The gate stack comprises a high-k dielectric layer; a first work function metal layer over the high-k dielectric layer; an oxide of the first work function metal layer over the first work function metal layer; and a second work function metal layer over the oxide of the first work function metal layer, in which the first and second work function metal layers have different compositions; and a gate electrode over the second work function metal layer.

Abstract: A display panel and an operation method of the display panel are provided. The display panel includes a display area and a frame area. The display area is configured to display an image. During a touch sensing period, the display area and the frame area emit an uplink signal to perform an active stylus touch detection operation.

Abstract: A transient voltage suppression device includes a P-type semiconductor layer, a first N-type well, a first N-type heavily-doped area, a first P-type heavily-doped area, a second P-type heavily-doped area, and a second N-type heavily-doped area. The first N-type well and the second N-type heavily-doped area are formed in the layer. The first P-type heavily-doped area is formed in the first N-type well. The first P-type heavily-doped area is spaced from the bottom of the first N-type well. The second P-type heavily-doped area is formed within the first N-type well and spaced from the sidewall of the first N-type well. The second P-type heavily-doped area is formed between the first P-type heavily-doped area and the second N-type heavily-doped area.

Abstract: Provided is a pre-conditioned mesenchymal stem cell (MSC), an exosome derived therefrom, and a cell-protective composition including the pre-conditioned MSC or the exosome. Also provided is a method for preparing the pre-conditioned MSC by contacting an MSC with an effective amount of ginkgolide A. Still provided is a method for promoting recovery or reducing death of damaged nerve cells, including administering to the damaged nerve cells a composition including the pre-conditioned MSC or the exosome.

Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data sate. The first random bit is then read from the MRAM cell.

Abstract: The present invention provides a photodiode, which includes: a light absorption substrate, a first electrode portion, a second electrode portion, an antireflection layer, and a distributed Bragg reflection layer. The antireflection layer is arranged to receive light to get into the light absorption substrate. The antireflection layer is arranged to receive light to get into the light absorption substrate, and the distributed Bragg reflection layer is arranged to reflect light transmitting through the light absorption substrate to exit from the light absorption substrate back to the light absorption substrate, in order to enhance the photocurrent and the spectrum sensitivity of the photodiode.

Abstract: A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.

Abstract: A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.

Abstract: A patch antenna includes a dielectric substrate formed by a high dielectric coefficient material covered with a soft material. The dielectric substrate has a first surface, an opposite second surface, and surrounding side surfaces there between. The patch antenna further includes a radiating metal arm formed on at least the first surface with a thin metal layer in a specific shape, a grounding metal plate disposed on the second surface, and a parasitic metal arm extending from the grounding metal plate towards the first surface via at least one of the side surfaces. The parasitic metal arm is approximate but not connected to the radiating metal arm. The radiation metal arm further includes an enclosed slot, together with the parasitic metal arm, improve the working bandwidth and high directivity of the antenna.

Abstract: A method of improving an efficiency of updating rule data stored in a block chain receives a rule updating request and obtains data as to the existing rule (rule data) in response to the rule updating request. Each obtained rule data is analyzed for compliance with a predefined rule strategy. When the obtained rule data is determined as complying, a priority level of each obtained rule data is confirmed. The obtained rule data is authenticated based on the priority level and a block chain authentication mechanism. When the obtained rule data is authenticated, the rule data stored in each block chain node in the block chain is updated. An electronic device and a computer readable storage medium applying the method are also provided.

Abstract: A method for profit sharing is provided. The method includes deciding a first sharing rate according to a first event information and a first category information; obtaining a first sharing amount according to the first sharing rate and a first shared profit of the first category information; deciding a second sharing rate according to a second event information and a second category information; obtaining a second sharing amount according to the second sharing rate and a second shared profit of the second category information; deciding a total sharing amount by summing up the first sharing amount and the second sharing amount; and returning the total sharing amount in response to receiving a request from a user device.

Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.

Abstract: A multi-channel transient voltage suppression device includes a semiconductor substrate, a semiconductor layer, at least two bidirectional transient voltage suppression structures, and at least one isolation trench. The semiconductor substrate, having a first conductivity type, is coupled to a grounding terminal. The semiconductor layer, having a second conductivity type opposite to the first conductivity type, is formed on the semiconductor substrate. The bidirectional transient voltage suppression structures are formed in the semiconductor layer. Each bidirectional transient voltage suppression structure is coupled to an input/output (I/O) pin and the grounding terminal. The isolation trench is formed in the semiconductor substrate and the semiconductor layer and formed between the bidirectional transient voltage suppression structures. The isolation trench has a height larger than the height of the semiconductor layer and surrounds the bidirectional transient voltage suppression structures.

Abstract: A method of treating pancreas damage is provided, the method comprises administrating a pharmaceutical composition to a subject in need thereof. The pharmaceutical composition comprises a plurality of pretreated adipose-derived stem cells and an ester type catechin, wherein the plurality of pretreated adipose-derived stem cells are cultured with the ester type catechin.

Abstract: A light-emitting module and a light-emitting diode are provided. The light-emitting diode includes an epitaxial light-emitting structure to generate a light beam with a broadband blue spectrum. A spectrum waveform of the broadband blue spectrum has a full width at half maximum (FWHM) larger than or equal to 30 nm. The spectrum waveform has a plurality of peak inflection points, and a difference between two wavelength values to which any two adjacent ones of the peak inflection points respectively correspond is less than or equal to 18 nm.