Abstract: An antenna-in-module includes a ground plate, three radiating elements, and two feed stubs. A first radiating element and a ground plate are arranged at an interval along a Z-axis and are disposed opposite to each other. The first radiating element and a second radiating element are arranged at an interval along an X-axis. A first gap between the first radiating element and the second radiating element extends along a Y-axis. A third radiating element and the second radiating element are arranged at an interval along the Z-axis and are disposed opposite to each other. At least a part of a first feed stub is disposed in a first aperture that includes space between the first gap and the ground plate. At least a part of a second feed stub is disposed in a second aperture that includes space between the second radiating element and the third radiating element.

Abstract: Embodiments of the present disclosure provide methods for forming merged source/drain features from two or more fin structures. The merged source/drain features according to the present disclosure have a merged portion with an increased height percentage over the overall height of the source/drain feature. The increase height percentage provides an increased landing range for source/drain contact features, therefore, reducing the connection resistance between the source/drain feature and the source/drain contact features. In some embodiments, the emerged source/drain features include one or more voids formed within the merged portion.

Abstract: A method includes forming a first transistor stack over a substrate. The first transistor stack includes: a first transistor of a first conductivity type, and a second transistor of a second conductivity type different from the first conductivity type. The second transistor is above the first transistor. A plurality of first conductive lines is formed in a first metal layer above the first transistor stack. The plurality of first conductive lines includes, over the first transistor stack, a power conductive line configured to route power to the first transistor stack, one or more signal conductive lines configured to route one or more signals to the first transistor stack, and a shielding conductive line configured to shield the routed one or more signals. The one or more signal conductive lines are between the power conductive line and the shielding conductive line.

Abstract: A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.

Abstract: An energy storage cabinet includes a frame supporting multiple battery packs and a cooling device. The frame includes a support with a pipe and a partition dividing an internal fluid passage of the pipe into a first flow channel and a second flow channel. Each battery pack has a first vent and a second vent. The second vent of a first battery pack is in communication with the second flow channel. The first vent of a second battery pack is in communication with the first flow channel. The cooling device produces a cool air entering the first vent of the first battery pack and the first flow channel. As the cool air passes through the first battery pack, the cool air is heated and becomes a warm air, which is then discharged into the second flow channel through the second vent.

Abstract: A battery pack includes a housing, a plurality of battery cells and a liquid filling device. The battery cells are disposed in the housing, and each of the battery cells includes two electrodes. The housing has a side opening. A lower edge of the side opening is positioned below the electrodes in a vertical direction. The liquid filling device is connected to the housing and is configured to fill a cooling liquid into the housing. The side opening of the housing is configured to allow excessive cooling liquid to be discharged out of the housing.

Abstract: A battery cell interconnection component includes a multi-layer structure and two holders. The multi-layer structure includes a plurality of metal strips in a stack arrangement. A gap is formed between any two immediately adjacent metal strips. The two holders fixedly clamp two ends of the multi-layer structure, and each of the two holders is configured to be electrically connected to an electrode of a battery cell.

Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Abstract: A method (of manufacturing a memory device) includes forming active regions extending in a first direction; over the active regions, doing as follows including, forming gate structures extending in a second direction perpendicular to the first direction, and forming contact-to-source/drain structures (MD structures) which extend in the second direction and are interspersed among corresponding ones of the gate structures; forming via-to-gate/MD (VGD) structures over corresponding ones of the gate structures and the MD structures; in a first metallization layer over the VGD structures, forming first front-side segments extending in the first direction and including one or more front-side routing (FRTE) segments; under the active regions, forming buried segment-to-source/drain structures (BVD structures); and in a first buried metallization layer under the BVD structures, forming first back-side segments extending in the first direction and including one or more first back-side power grid (BPG) segments.

Abstract: A device includes a plurality of tracks, wherein at least one of the plurality of tracks comprises a first power rail for a first voltage. The device further includes a first via in electrical contact with the power rail. The device further includes a first contact in electrical contact with the first via. The device further includes a first transistor in electrical contact with the first contact. The device further includes a second transistor in electrical isolation with the first transistor. The device further includes a second contact in electrical contact with the second transistor. The device further includes a second via in electrical contact with the second contact. The device further includes a second power rail in electrical contact with the second via, wherein the second power rail is configured to carry a second voltage.

Abstract: A roller input device includes a substrate, a bracket assembly, a roller seat, and a stopping member. The substrate has a top surface provided with a click button switch and a first tilt button switch. The bracket assembly and the roller seat are disposed on the substrate. The roller seat is pivotally connected to the bracket assembly. The stopping member is connected to the roller seat and has a first stopping portion. A first initial spacing is between the first stopping portion and the top surface. When the roller seat is at a pressing position, the first initial spacing is reduced to a first spacing being less than a first pressing stroke of the first tilt button switch. When the roller seat is at a first tilt position, the first initial spacing is reduced to a second spacing being less than a click pressing stroke of the click button switch.

Abstract: A laser welding mechanism includes a main body having a space and two securing devices which are respectively attached to two ends of the body. A linkage assembly includes a bearing and a linkage tube. A refraction mirror unit includes two mirrors connected to the linkage tube of the linkage assembly. A laser unit is pivotally connected to a swinging member which is connected to the linkage tube of the linkage assembly. A drive unit including a motor, a driving gear, and a driven gear. A rotation unit is connected to the swinging member of the laser unit. The laser unit rotates relative to the first workpiece and the second workpiece during welding, ensuring a stable rotation at the joining faces of the two workpieces.

Abstract: A memory device includes a first word line and a second word line. A first portion of the first word line is formed in a first metal layer, a second portion of the first word line is formed in a second metal layer above the first metal layer, and a third portion of the first word line is formed in a third metal layer below the second metal layer. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The first portion, the second portion, and the third portion of the first word line have sizes that are different from each other, and the first portion and the second portion of the second word line have sizes that are different from each other.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a source/drain epitaxial feature disposed over a substrate, and the source/drain epitaxial feature includes about 0.002 atomic percent to about 0.02 atomic percent of aluminum. The structure further includes a first semiconductor layer in contact with the source/drain epitaxial feature and a gate electrode layer disposed over the first semiconductor layer.

Abstract: The present disclosure relates a device. The device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure. An oxide semiconductor is disposed along the second side of the ferroelectric structure and has a first semiconductor conductivity type. A source and a drain are disposed on the oxide semiconductor. A semiconductor layer is arranged on the oxide semiconductor between sidewalls of the source and the drain. The semiconductor layer includes a semiconductor material having a second semiconductor conductivity type that is different than the first semiconductor conductivity type. The semiconductor layer includes p-doped silicon, p-doped germanium, n-doped silicon, or n-doped germanium.

Abstract: An integrated circuit device includes a first-type active-region semiconductor structure, a second-type active-region semiconductor structure stacked with the first-type active-region semiconductor structure, a front-side power rail in a front-side conductive layer, and a back-side power rail in a back-side conductive layer. The integrated circuit device also includes a source conductive segment intersecting the first-type active-region semiconductor structure at a source region of a transistor, a back-side power node in the back-side conductive layer, and a top-to-bottom via-connector. The source conductive segment is conductively connected to the front-side power rail through a front-side terminal via-connector. The top-to-bottom via-connector is connected between the source conductive segment and the back-side power node.

Abstract: Compounds, compositions and methods are provided for modulating the activity of EP2 and EP4 receptors, and for the treatment, prevention and amelioration of one or more symptoms of diseases or disorders related to the activity of EP2 and EP4 receptors. In certain embodiments, the compounds are antagonists of both the EP2 and EP4 receptors.

Abstract: The present application provides a proximity detection circuit and a proximity detection method with compensation. The proximity detection circuit comprises a detection circuit, a baseline processing circuit and a proximity sensing circuit. The detection circuit generates a detection data and a reference data. The proximity sensing circuit generates a proximity signal according to a proximity threshold, the detection data and a baseline data generated from the baseline processing circuit, and the proximity detection circuit and the proximity detection method compensate the baseline data or the proximity threshold according to the reference data. The condition of misjudgment may be avoided under the influence of environmental factors.