Abstract: Described herein, inter alia, are LPAR1 antagonists and uses thereof.

Abstract: A computing device obtains an image depicting a watch and performs segmentation on the watch in the image to generate a segmented watch region comprising a watch case region, a first watch strap region, and a second watch strap region. The computing device generates a three-dimensional (3D) mesh according to the watch case region, the first watch strap region, the second watch strap region, and a pre-defined skeleton containing at least one straight part and at least two curved parts. The computing device generates texture attributes according to the segmented watch and applies the texture attributes to the 3D mesh to generate a textured 3D watch object. The computing device renders the textured 3D watch object in an augmented reality display.

Abstract: An optical imaging lens proofed against field curvatures, in an imaging module, and the module being used in an electronic device, is, from an object side to an image side, composed of a first lens with a positive refractive power, a second lens, a third lens, a fourth lens with a negative refractive power, a fifth lens, and a sixth lens with a negative refractive power. The optical imaging lens satisfies the formula ?3 mm?1<FNO/f6<?0.1 mm?1, ?0.065 mm/°<f6/FOV<?0.03 mm/°, wherein FNO is a F-number of the optical imaging lens, f6 is a focal length of the sixth lens, and FOV is a maximum field of view of the optical imaging lens.

Abstract: A cyclic power generation and storage system with dynamic battery switching capability is provided, comprising: a power supply modules, a driving module, a transmission module, a plurality of power generation modules, a control module, and a plurality of power storage modules. The present invention can dynamically switch in battery packs to provide a stable power to an electrical device, as well as, switch in a battery or battery pack for recharging with the power generated by the power generation modules. The power storage module having a power management unit, together with the control module, uses the detection result from the power detection unit of the power storage module to dynamically adjust the power generation, distribution, storage, and usage to improve the overall efficiency of the present invention.

Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a first source/drain feature and a second source/drain feature, a plurality of semiconductor layers vertically stacked and disposed between the first and second source/drain features, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, and an interfacial layer (IL) disposed between the gate electrode layer and one of the plurality of the semiconductor layers, wherein a topmost semiconductor layer of the plurality of the semiconductor layers has a first length, and the IL has a second length greater than the first length.

Abstract: A memory device includes a semiconductor substrate having an active region, and a word line extending across the active region. The memory device also includes a first source/drain region and a second source/drain region disposed in the active region and on opposite sides of the word line. The memory device further includes a bit line contact disposed over and electrically connected to the first source/drain region. The bit line contact has a tapered profile. In addition, the memory device includes a capacitor contact disposed over and electrically connected to the second source/drain region.

Abstract: According to some embodiments of the disclosure, a semiconductor structure includes a first alignment region defined in a substrate layer and a first frame at edges of the first alignment region. A first alignment mark is in the first alignment region and bordered by the first frame. According to some embodiments of the disclosure, a method of fabricating a semiconductor structure includes forming an isolation structure over a substrate layer in a first alignment region. A process layer is formed over the isolation structure. A patterned mask is formed over the process layer. The process layer is patterned using the patterned mask as a template to form a first frame at edges of the first alignment region and a first alignment mark in the first alignment region and bordered by the first frame.

Abstract: A memory device includes a semiconductor substrate having an active region, and a word line extending across the active region. The memory device also includes a first source/drain region and a second source/drain region disposed in the active region and on opposite sides of the word line. The memory device further includes a bit line contact disposed over and electrically connected to the first source/drain region. The bit line contact has a tapered profile. In addition, the memory device includes a capacitor contact disposed over and electrically connected to the second source/drain region.

Abstract: A memory device includes a first memory array comprising first memory cells; a second memory array comprising second memory cells; a third memory array comprising third memory cells, the second memory array interposed between the first memory array and the third memory array along a lateral direction; a first bit line segment extending along the lateral direction and coupled to each of the first memory cells; a second bit line segment extending along the lateral direction and coupled to each of the second memory cells; and a third bit line segment extending along the lateral direction and coupled to each of the third memory cells. The first bit line segment is formed in a first metallization layer, the second bit line segment is formed in a second metallization layer, and the third bit line segment is formed in a third metallization layer.

Abstract: A method of decoding video data is provided. The method includes: receiving the video data; determining, from an image frame of the video data, a block unit; determining a first intra prediction of the block unit based on a decoder-side intra mode derivation (DIMD) mode; determining a second intra prediction of the block unit based on an intra prediction mode other than the DIMD mode; generating a third intra prediction based on the first intra prediction and the second intra prediction; and reconstructing the block unit based on the third intra prediction. In addition, an electronic device using the method is also provided.

Abstract: The present disclosure, in some embodiments, relates to a ferroelectric memory device. The ferroelectric memory device includes a multi-layer stack disposed on a substrate. The multi-layer stack has a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. A plurality of oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.

Abstract: The present disclosure provides a motor including a stator, a rotor and a first circuit board. The stator includes a winding assembly including a plurality of coils. A conductive element is extended out from the winding assembly and is electrically connected to a first electrical connector. The first electrical connector penetrates through a pillow of the stator and is electrically connected to the first circuit board. The motor further includes a second circuit board electrically connected to the first circuit board, and a first insulation plate, a second insulation plate and a third insulation plate for fixing and protecting the circuit boards. The motor also includes a clip for fixing and heat dissipating an electronic component disposed on the second circuit board.

Abstract: A semiconductor device includes a substrate, a bit line structure formed over and protruding from the substrate, a spacer structure formed on and extending along sidewall of the bit line structure, and a landing pad disposed on the bit line structure and covering the slope. The spacer structure includes a first segment near a top of the spacer structure with a slope and a second segment beneath the first segment. A first segment consists of a first spacer layer contacting the bit line structure and a third spacer layer contacting the first spacer layer. A second segment consists of the first spacer layer contacting the bit line structure, a second spacer layer contacting the first spacer layer, and the third spacer layer contacting the second spacer layer, and the second segment is capped with the first segment.

Abstract: A method of encoding video data is provided. The method determines a block unit of an image frame of the video data. The method determines, for the block unit, a first merge candidate list including multiple merge candidates, and identifies multiple merge subgroups from the first merge candidate list. The method determines multiple first cost values each corresponding to one of the merge candidates, and determines an arrangement of the merge candidates in each of the merge subgroups based on the first cost values. The method determines a second merge candidate list by selecting, from each of the merge subgroups, a first K merge candidates of the merge candidates ordered based on the arrangements. Then, the method selects one of the merge candidates in the second merge candidate list to predict the block unit and encodes one or more merge indices into a bitstream based on the selected merge candidate.

Abstract: A method of decoding video data performed by an electronic device is provided. The method receives the video data and determines a block unit from a current frame included in the video data. The method further determines an intra prediction mode from a plurality of intra default modes, determine a cross-component prediction (CCP) merge list of the block unit including a plurality of CCP merge candidates; and selecting one of the CCP merge candidates for the block unit to determine a prediction model of the selected CCP merge candidate. The method then predicts the block unit using the prediction model of the selected CCP merge candidate to generate a first prediction block, predicts the block unit based on the intra prediction mode to generate a second prediction block, and reconstructs the block unit based on the first prediction block and the second prediction block.

Abstract: An array substrate includes a substrate, a compensation layer, an insulating layer and an active layer. The compensation layer is disposed on a side of the substrate. The insulating layer is disposed on a side of the compensation layer away from the substrate and covers the compensation layer. The active layer is disposed on a side of the insulating layer away from the substrate. A vertical projection of the compensation layer on the substrate overlaps a vertical projection of the active layer on the substrate, and the compensation layer is configured to compensate for a threshold voltage of a thin-film transistor of the array substrate.

Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. The oxide semiconductor has a first semiconductor type. A source region and a drain region are disposed on the oxide semiconductor. The gate structure is laterally between the source region and the drain region. A polarization enhancement structure is arranged on the oxide semiconductor between the source region and the drain region. The polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type that is different than the first semiconductor type.

Abstract: A static random access memory includes a first and second memory cell array, a first word line, a bit line, a bit line bar, a primary driver circuit, and a first and second supplementary driver circuit. The first supplementary driver circuit is configured to pull a voltage of a first signal of the bit line or a second signal of the bit line bar to a first voltage level during a write operation in response to a supplementary driver circuit enable signal. The second supplementary driver circuit is configured to sense the voltage of the first or second signal. The second supplementary driver circuit includes a first pass-gate transistor. A first terminal of the first pass-gate transistor is coupled to a reference voltage supply. A second terminal of the first pass-gate transistor is electrically floating. A third terminal of the first pass-gate transistor is coupled to a first node.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: An electronic device includes a decoupling member, a first radiator, a second radiator, a first feed unit, a second feed unit, and a rear cover. A gap is formed between the first radiator and the second radiator, the decoupling member is indirectly coupled to the first radiator and the second radiator, and the decoupling member is disposed on a surface of the rear cover. The decoupling member does not overlap a first projection, and the first projection is a projection of the first radiator in a first direction. The decoupling member does not overlap a second projection, and the second projection is a projection of the second radiator in the first direction. The first direction is a direction perpendicular to a plane on which the rear cover is located.