Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.

Abstract: A semiconductor structure includes at least one sub-word line driver. The sub-word line driver includes a plurality of first active areas and a main-word line. The main-word line includes a plurality of first gates and a plurality of second gates interconnected. The plurality of first gates correspond to the plurality of first active areas. An extension direction of the plurality of first gates in the main-word line and/or an extension direction of at least part of the second gates in the main-word line intersects both a first direction and a second direction. The first direction is parallel to a direction in which the first active areas extend, and the second direction is parallel to a plane in which the first active areas are located and is perpendicular to the first direction.

Abstract: The present disclosure provides a semiconductor package structure, relating to the technical field of semiconductors. The semiconductor package structure includes: a substrate; and at least one chip stack structure provided on the substrate, where the at least one chip stack structures include a plurality of first chips vertically stacked, each of the first chips includes a first conductive plug set, a connection layer is provided between two adjacent first chips, a wire structure is provided in the connection layer, the wire structure is electrically connected to the first conductive plug sets in two first chips adjacent to the wire structure, projections of two first conductive plug sets electrically connected to a same wire structure on the substrate are staggered from each other, and the first conductive plug sets in the plurality of first chips are connected in series through the wire structures to form an inductor structure.

Abstract: A semiconductor structures and a method for forming the same are provided. The semiconductor structure includes first nanostructures and second nanostructures spaced apart from the first nanostructures in a first direction. A left-most point of the first nanostructures and a left-most point of the second nanostructures has a first distance in the first direction. The semiconductor structure further includes first source/drain features attached to opposite sides of the first nanostructures in a second direction being orthogonal to the first direction and third nanostructures and fourth nanostructures spaced apart from the third nanostructures in the first direction. A left-most point of the third nanostructures and a left-most point of the fourth nanostructures has a second distance in the first direction. In addition, the third nanostructures are wider than the first nanostructures in the first direction, and the first distance is smaller than the second distance.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A method includes depositing a photoresist layer over a target layer, the photoresist layer comprising an organometallic material; exposing the photoresist layer to an extreme ultraviolet (EUV) radiation; developing the exposed photoresist layer to form a photoresist pattern; forming a spacer on a sidewall of the photoresist pattern; removing the photoresist pattern; after removing the photoresist pattern, patterning the target layer through the spacer.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. According to embodiments of the present disclosure, a height of the work function layer, especially a height of the second portion of the work function layer, is significantly increased, and a height of the first gate material layer is significantly reduced, so that the height ratio of the second portion of the work function layer to the first gate material layer to the second gate material layer is maintained at 3 to 8:1 to 1.5:1; therefore, it can be ensured that the work function of the WL groove filling material layer of the recessed gate structure with a small WL width will be significantly increased, thereby greatly weakening the row hammer effect at the bottom of the WL groove and obviously reducing the GIDL effect at the upper part of the WL groove.

Abstract: A surgical robot including at least one contact module, a control connection module, at least one first robotic arm, and at least one grip control device. A first transmission member of the control connection module drives the control module through a first transmission connecting member. A first shaft member of the first robotic arm is connected with the first transmission member while the grip control device is connected with the first robotic arm by a transmission interface. A force sensing member of the first robotic arm detects a first reaction force from the contact module so that the first robotic arm sends a feedback control signal to the grip control device to control a grip driving member to generate a force feedback for allowing a grip portion to move. Thereby, users can feel movement of the grip portion caused by the force feedback to avoid accidental iatrogenic injuries.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Abstract: The embodiments of the present disclosure provide a memory and a manufacturing method of a memory. The memory includes first fins and second fins disposed on a substrate, a dielectric layer covering tops of the first fins and side wall surfaces exposed by an isolating structure, and work function layers disposed on a surface of the dielectric layer. In a direction parallel to an arrangement direction of the first fins and the second fins, the work function layers on the side walls where the adjacent first fins are opposite are provided with a first thickness, and the work function layers on the side walls where the first fins face towards the second fins are provided with a second thickness. The first thickness is greater than the second thickness.

Abstract: Metal-comprising resist layers (for example, metal oxide resist layers), methods for forming the metal-comprising resist layers, and lithography methods that implement the metal-comprising resist layers are disclosed herein that can improve lithography resolution. An exemplary method includes forming a metal oxide resist layer over a workpiece by performing deposition processes to form metal oxide resist sublayers of the metal oxide resist layer over the workpiece and performing a densification process on at least one of the metal oxide resist sublayers. Each deposition process forms a respective one of the metal oxide resist sublayers. The densification process increases a density of the at least one of the metal oxide resist sublayers. Parameters of the deposition processes and/or parameters of the densification process can be tuned to achieve different density profiles, different density characteristics, and/or different absorption characteristics to optimize patterning of the metal oxide resist layer.

Abstract: A memory includes a substrate; a plurality of bit lines on the substrate, which are parallel to each other and extend in a first direction; a plurality of active pillars on the bit lines, bottom ends of which are connected to the bit lines; a plurality of word lines parallel to each other and extending in a second direction, which surround outer sidewalls of the active pillars, and expose top ends of the active pillars, the active pillars and the word lines jointly constitute vertical memory transistors of the memory; and a plurality of capacitors and a plurality of connecting pads, each of the capacitors is located on each of the active pillars, each of the connecting pads is located between the active pillar and the capacitor.

Abstract: Embodiments of the present disclosure relate to the semiconductor field, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, first gates and second gates, and a first conductive channel; where the substrate includes first active regions and two second active regions located between adjacent first active regions, the first active region defines a pull-down transistor, the second active region defines a pull-up transistor; the first active region has a first source region, a first channel region, and a first drain region arranged along a second direction.

Abstract: A semiconductor structure includes: a substrate, a first conductive layer disposed on the substrate, a second conductive layer disposed on a surface of the first conductive layer away from the substrate, and third conductive layers covering side walls of the first conductive layer and in contact with the second conductive layer. Contact resistance between the third conductive layers and the second conductive layer is less than contact resistance between the first conductive layer and the second conductive layer.

Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes: providing a substrate, and forming a first isolating layer, a first stabilizing layer, a second isolating layer and a second stabilizing layer, which are sequentially stacked onto one another, on the substrate; forming a through hole penetrating through the first isolating layer, the first stabilizing layer, the second isolating layer and the second stabilizing layer, and forming a lower electrode on a side wall and a bottom portion of the through hole; removing a portion of a thickness of the second stabilizing layer to expose a portion of the lower electrode; forming a mask layer on a side wall of the exposed lower electrode; and etching the second stabilizing layer by using the mask layer as a mask to form a first opening.

Abstract: A semiconductor structure includes a storage chip, a control chip, and a capacitor structure. The storage chip includes an array area. The control chip includes a peripheral area. The control chip and the storage chip are connected in a face-to-face bonding manner. The capacitor structure is located on a surface, away from a bonding surface, of the storage chip. The capacitor structure includes capacitors electrically connected to corresponding transistors in the array area.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes an aromatic di-dentate ligand, a transition metal coordinated to the aromatic di-dentate ligand, and an extreme ultraviolet (EUV) cleavable ligand coordinated to the transition metal. The aromatic di-dentate ligand includes a plurality of pyrazine molecules.