Abstract: A semiconductor structure includes a substrate, a via, a conductive pillar, and a core layer. The via is located in the substrate. The conductive pillar is located in the via, and the conductive pillar is provided with a groove extended inwards from an upper surface of the conductive pillar. The core layer is located in the groove, a Young modulus of the core layer is less than that of the conductive pillar.

Abstract: The present application provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a stacked structure, the stacked structure includes a first chip and a second chip; forming a through silicon via (TSV) in the stacked structure, the TSV includes a first part and a second part communicating with the first part, a sidewall of the first part is a vertical sidewall, and a sidewall of the second part is an inclined sidewall; forming an insulating layer on the sidewall of the first part; and forming a conductive layer in the TSV.

Abstract: A method for forming a thermal conduction structure includes: a substrate is provided, at least a dielectric layer being formed on the substrate; a Through Silicon Via (TSV) and at least one silicon blind hole are formed, where the at least one silicon blind hole is located on at least one side of the TSV, the TSV penetrates through the substrate and the dielectric layer, and each silicon blind hole does not penetrate through the substrate.

Abstract: The present disclosure relates to a layout structure forming method of a sense amplifier and a layout structure of a sense amplifier. The method includes: providing a first active region layout structure layer, the first metal contact pattern layer includes a first metal contact pattern and a second metal contact pattern that are located on two opposite sides of the first pattern region; the first conductive wire pattern layer includes a first conductive wire pattern covering the first metal contact pattern and the second metal contact pattern; and the first connection hole pattern layer includes a plurality of connection hole designs, and the connection hole designs are connected to form a connection structure connected to the first metal contact pattern layer.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes: a substrate is provided; bit line contact holes spaced apart from each other, bit line contacts each in contact with a part of a respective one of the bit line contact holes, and bit line structures are formed on the substrate, where each of the bit line structures includes at least a conductive layer and an insulating cap layer, and the insulating cap layer is located on the conductive layer; first insulating layers completely filling the bit line contact holes are formed inside the bit line contact holes; and insulation structures with air interlayers are formed on two side walls of the bit line structures, where a height of each of the air interlayers is greater than a height of the conductive layer of each of the bit line structures.

Abstract: The present application provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a stacked structure, the stacked structure includes a first chip and a second chip; forming a through silicon via (TSV) in the stacked structure, the TSV includes a first part and a second part communicating with the first part, a sidewall of the first part is a vertical sidewall, and a sidewall of the second part is an inclined sidewall; forming an insulating layer on the sidewall of the first part; and forming a conductive layer in the TSV.

Abstract: A semiconductor structure includes a Through Silicon Via (TSV) and a protective ring disposed outside the TSV; the protective ring includes at least two protective layers arranged in parallel and surrounding the TSV; each of the protective layers includes a first protective structure and second protective structures disposed surrounding the first protective structure; the first protective structure is a polygonal structure; a number of sides of the polygonal structure is greater than or equal to 4; and the second protective structures are disposed on an inner side and an outer side of each corner area of the polygonal structure.

Abstract: The present disclosure relates to a method of forming a sense amplifier and a layout structure of a sense amplifier. The method includes: providing a first active region pattern layer, the first active region pattern layer includes a bridge pattern, and a first active region pattern region and a second active region pattern region; the first active region pattern region includes a first active region pattern for defining a first pull-down transistor of a first memory cell structure; the second active region pattern region includes a first symmetrical active region pattern for defining a second pull-down transistor of a second memory cell structure; and the first active region pattern and the first symmetrical active region pattern are adjacent to each other and connected through the bridge pattern, a source of the first pull-down transistor and a source of the second pull-down transistor are electrically connected through the bridge pattern.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. According to embodiments of the present disclosure, a height of the work function layer, especially a height of the second portion of the work function layer, is significantly increased, and a height of the first gate material layer is significantly reduced, so that the height ratio of the second portion of the work function layer to the first gate material layer to the second gate material layer is maintained at 3 to 8:1 to 1.5:1; therefore, it can be ensured that the work function of the WL groove filling material layer of the recessed gate structure with a small WL width will be significantly increased, thereby greatly weakening the row hammer effect at the bottom of the WL groove and obviously reducing the GIDL effect at the upper part of the WL groove.

Abstract: A semiconductor structure and a method for fabricating a semiconductor structure are provided. In the semiconductor structure, a side of a film layer structure facing away from a substrate is provided with a wiring layer, a side of the substrate facing away from the film layer structure is provided with a connecting hole extending to the wiring layer, and an insulating layer is arranged on a hole wall of the connecting hole. A barrier ring is arranged on the insulating layer, a center line of the barrier ring is arranged collinearly with a center line of the connecting hole, and diffusibility of the barrier ring is less than diffusibility of the wiring layer. A connecting post joined to the wiring layer is arranged in the connecting hole.

Abstract: A semiconductor structure includes a substrate, a TSV structure and a first protection structure. The substrate has a first region and a second region arranged adjacent to each other, and the first region comprises a functional device. The TSV structure is arranged in the second region and electrically connected to the functional device. The first protection structure is arranged around the TSV structure and electrically connected to the TSV structure. The first protection structure is located between the TSV structure and the functional device.

Abstract: Provided are a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes: a through silicon via and a shielding structure disposed at an outer side of the through silicon via, in which the shielding structure includes at least two non-closed annular shielding layers surrounding the through silicon via and at least one conductive plug configured to connect two adjacent ones of the non-closed annular shielding layers; the at least two non-closed annular shielding layers and the at least one conductive plug are alternately distributed along an extending direction of the through silicon via and sequentially connected to form a conductive path, and current flow directions in two adjacent ones of the non-closed annular shielding layers in the conductive path are opposite.

Abstract: A semiconductor structure manufacturing method includes: providing a substrate; forming, on the substrate, a stack structure including a sacrificial layer and a support layer which are alternately stacked on each other; forming a capacitance hole in the stack structure; forming a first electrode layer on a side wall and a bottom of each capacitance hole; forming a first dielectric layer on an inner surface of the first electrode layer; forming, on the stack structure, an opening from which the sacrificial layer is exposed, and removing the sacrificial layer through the opening; forming a second dielectric layer on an inner surface of the first dielectric layer and an outer surface of the first electrode layer; and forming a second electrode layer on an inner surface and an outer surface of the second dielectric layer.

Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes: providing a substrate, and forming a first isolating layer, a first stabilizing layer, a second isolating layer and a second stabilizing layer, which are sequentially stacked onto one another, on the substrate; forming a through hole penetrating through the first isolating layer, the first stabilizing layer, the second isolating layer and the second stabilizing layer, and forming a lower electrode on a side wall and a bottom portion of the through hole; removing a portion of a thickness of the second stabilizing layer to expose a portion of the lower electrode; forming a mask layer on a side wall of the exposed lower electrode; and etching the second stabilizing layer by using the mask layer as a mask to form a first opening.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate having a trench therein, the trench including a corner between a bottom and a sidewall, the corner protruding in a direction away from an opening of the trench; a first isolation layer, covering a surface of the sidewall, a surface of the corner and a surface of the bottom; a second isolation layer, covering a surface of the first isolation layer, a hardness of a material of the second isolation layer being greater than that of the first isolation layer; and a stress adjustment layer, located in the first isolation layer between the corner and the second isolation layer, a hardness of the stress adjustment layer being greater than that of the first isolation layer.

Abstract: A transistor structure of a semiconductor memory device comprises: an active area having a plurality of trenches and a substrate surface, the trenches having openings oriented toward the substrate surface; a plurality of gate structures embedded in the trenches, wherein the substrate surface comprises source regions located on outer sides of the gate structures and a drain region located between the gate structures; node contacts each disposed on one of the source regions; a bit line contact disposed on the drain region and connectable to a bit line, the node contacts sharing the bit line contact through adjacent gate structures, wherein the drain region comprises a first ion implantation layer extending inwardly from the bit line contact, each of the source regions comprising a second ion implantation layer extending inwardly from a corresponding node contact, the first ion implantation layer being deeper than the second ion implantation layer.

Abstract: A bonding pad structure and a method thereof includes: a base metal layer formed on a substrate; first conductive vias arranged in a peripheral region of the base metal layer; an intermediate buffer layer formed above the base metal layer, the intermediate buffer layer spaced from and aligned with the base metal layer, the first conductive vias vertically connecting the base metal layer and the intermediate buffer layer; second conductive vias arranged in a peripheral region of the intermediate buffer layer; a surface bonding layer formed above the intermediate buffer layer, the surface bonding layer spaced from and aligned with the intermediate buffer layer, the second conductive vias vertically connecting the intermediate buffer layer and the surface bonding layer, the intermediate buffer layer comprising a mesh structure, and the first conductive vias and the second conductive vias not vertically aligned with a central region of the intermediate buffer layer.

Abstract: Provided are a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method includes: a substrate is provided, which includes a first area and a second area set adjacent to each other; multiple trenches, which are arranged at intervals along a first direction, are formed in both the first area and the second area of the substrate; a word line (WL) is formed in each of the multiple trenches, a feature size of the WL in the first area is different from that of the WL in the second area; and a contact structure is formed on the WL with the greater feature size.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, in which a plurality of active areas arranged in an array are provided; buried word lines located in the substrate, in which each of the active areas intersects with two of the buried word lines; grooves located in an upper surface of the substrate, in which each of the grooves is located between two of the buried word lines in each of the active areas; bit line contact layers filling the grooves; insulating layers distributed between two of the grooves, in which a thickness between upper surfaces of the insulating layers and the upper surface of the substrate is smaller than a thickness between upper surfaces of the bit line contact layers and the upper surface of the substrate; and bit line conducting layers, covering the bit line contact layers and the insulating layers.

Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes a chemical formula of MaXbLc, where M is a metal, X is a multidentate aromatic ligand that includes a pyrrole-like nitrogen and a pyridine-like nitrogen, L is an extreme ultraviolet (EUV) cleavable ligand, a is between 1 and 2, b is equal to or greater than 1, and c is equal to or greater than 1.