Abstract: A gripping device comprises a base, a first finger rotatably or movably connected to the base, and a second finger connected to the base. The first finger and the second finger are capable of selectively entering an opened gripping mode and a closed gripping mode to grip an object. In the opened gripping mode, the first and second fingers grip the object from the same side of the object. In the closed gripping mode, the first and second fingers grip the object from different sides of the object.

Abstract: A split-gate MOSFET includes first and second epitaxial layers, first, second, and third gates, a gate oxide layer, a trench oxide layer, and a trench implantation region formed on a substrate in order. The second epitaxial layer has a doping concentration greater than that of the first epitaxial layer. A plurality of trenches is in the first and second epitaxial layers. Both the first and second gates are located in each of the trenches in a cell region. The third gates are located in each of the trenches in a terminal region. The third gate closest to the cell region is grounded, and the others are floating. The gate oxide layer is disposed between the first and second gates. The trench oxide layer is located between the first gate and the first epitaxial layer and located between the trench surface and the third gate. The trench implantation region is located in the first epitaxial layer at the bottom of the trench and has a doping concentration less than that of the first epitaxial layer.

Abstract: A gripping device comprises a base, a first finger rotatably or movably connected to the base, and a second finger connected to the base. The first finger and the second finger are capable of selectively entering an opened gripping mode and a closed gripping mode to grip an object. In the opened gripping mode, the first and second fingers grip the object from the same side of the object. In the closed gripping mode, the first and second fingers grip the object from different sides of the object.

Abstract: This invention relates to molecular catalysts and chemical reactions utilizing the same, and particularly to molecular catalysts for efficient catalytic oxidation of hydrocarbons, such as hydrocarbons from natural gas. The molecular catalytic platform provided herein is capable of the facile oxidation of hydrocarbons, for example, under ambient conditions such as near room temperature and atmospheric pressure.

Abstract: The present invention discloses an omnidirectional movement control system, having a move signal generator for generating a plurality of movement signals based on a plurality of first position signals and a plurality of second position signals, and an omnidirectional movement controller for generating a plurality of pulse width modulation signals and a plurality of motor direction change signals based on the movement signals and a plurality of motor encoding disc signals, and a driving circuit for driving motors to rotate a plurality of omnidirectional wheels based on the pulse width modulation signals and the motor direction change signals, such that a mobile platform can be moved in any direction and rotated in different directions, so as to provide excellent mobility and flexibility to the mobile platform.

Abstract: The present invention discloses an omnidirectional movement control system, having a move signal generator for generating a plurality of movement signals based on a plurality of first position signals and a plurality of second position signals, and an omnidirectional movement controller for generating a plurality of pulse width modulation signals and a plurality of motor direction change signals based on the movement signals and a plurality of motor encoding disc signals, and a driving circuit for driving motors to rotate a plurality of omnidirectional wheels based on the pulse width modulation signals and the motor direction change signals, such that a mobile platform can be moved in any direction and rotated in different directions, so as to provide excellent mobility and flexibility to the mobile platform.

Abstract: A P-channel memory is provided. Each memory unit is constructed of a substrate, a gate structure, a first charge trapping layer, a second charge trapping layer, a first source/drain, and a second source/drain. The gate structure is located above the substrate. The first charge trapping layer and the second charge trapping layer are located on both sidewalls of the gate structure for storing two bit of data in a single memory unit. The first source/drain and the second source/drain are located in the substrate on both sides of the gate structure.

Abstract: A method of operating a P-channel memory is described. The P-channel memory includes a substrate, a gate formed over the substrate, a charge trapping structure disposed between the substrate and the gate, and the first and second sources/drains formed in the substrate adjacent to two sides of the charge trapping structure. An erasing operation is performed by applying a first voltage to the second source/drain, applying a second voltage to the first source/drain, applying a third voltage to the gate, and applying a forth voltage to the substrate. Hot holes are injected in the charge trapping structure to erase the P-channel memory by the tertiary hot hole mechanism. The absolute value of the voltage differential between the third and the forth voltages is equal to, or less than 6V, and the second voltage is smaller than the third voltage.

Abstract: A semiconductor device is provided. The semiconductor device is suitable for an electrostatic discharge protection circuit. The semiconductor device includes a gate structure, an N-type source region, an N-type well region, an N-type drain region, and an N-doped region. Wherein, the gate structure comprises a gate and a gate oxide layer. The gate oxide layer is disposed between the gate and a substrate. In addition, the N-type source region is disposed in the substrate at one side of the gate, and the N-type well region is disposed in the substrate at another side of the gate. The N-type drain region is disposed in the substrate between the N-type well region and the gate structure. The N-type drain region has a first toothed part disposed in the N-type well region. The N-doped region is disposed in the N-type well region, and the N-doped region has a second toothed part.

Abstract: A method of operating a P-channel memory is described. The P-channel memory includes a substrate, a gate formed over the substrate, a charge trapping structure disposed between the substrate and the gate, and the first and second sources/drains formed in the substrate adjacent to two sides of the charge trapping structure. An erasing operation is performed by applying a first voltage to the second source/drain, applying a second voltage to the first source/drain, applying a third voltage to the gate, and applying a forth voltage to the substrate. Hot holes are injected in the charge trapping structure to erase the P-channel memory by the tertiary hot hole mechanism. The absolute value of the voltage differential between the third and the forth voltages is equal to, or less than 6V, and the second voltage is smaller than the third voltage.

Abstract: A test key includes a substrate, a deep trench capacitor formed in the substrate, and at least one active region defined on the substrate. The active region comprises a first region, a second region and an ion well. A thermal oxide layer is formed in the first region. A top-thin oxide layer is formed in the second region. The second region overlaps with the deep trench capacitor. At least one word line partially overlapping with the top-thin oxide layer. The ion well is electrically connected with a polysilicon electrode of the deep trench capacitor. The thermal oxide layer within the first region does not overlap with any word line.

Abstract: The present invention provides a method to manufacture a trench DRAM. The present method can avoid the latch-up phenomenon of a transistor, and can efficiently increase the ability of storing charge of a capacitor to avoid the soft errors caused by &agr; particles. In this method, an SOI is used to manufacture the trench DRAM. Because a dielectric layer in SOI separates the transistor from the substrate, the latch-up phenomenon can be avoided. By using oxygen-ion implantation, silicon layers can be divided, and elements can adequately be separated from each other.

Abstract: A memory module stores digital data. The memory module has many memory cells biased by a voltage source. Each memory cell has an access transistor electrically connected to a word line and a bit line for receiving bits from the bit line when the word line turns on the access transistor, a switching circuit electrically connected to the access transistor, and a capacitor electrically connected to the switching circuit. The switching circuit turns on or off according to the bit from the access transistor. The capacitor stores charge supplied by the switching circuit when the switching circuit turns on. The capacitor stores charge supplied by the voltage source when the switching circuit turns off. When the access transistor turns off, the switching circuit or the voltage source provides charge to the capacitor to sustain the voltage level of the capacitor to compensate for charge leakage of the capacitor.

Abstract: First of all, a semiconductor substrate is provided. On the semiconductor substrate, a word line is formed and covered with a insulating layer. Next, forming a connected device in the insulating layer to connect with the first conducting line layer. In order, a pinned layer is then deposited along the first insulating layer and the connected device. On top of the pinned layer, an insulating tunnel barrier layer is formed. Then a free layer is deposited on the insulating tunnel barrier layer. There is a single large MTJ that covers the entire surface of the first insulating layer on the conducting line layer. This large MTJ is then patterned into a small MTJ by etching process and through the free layer to the surface of the insulating tunnel barrier layer. Subsequently, the small MTJ are then covered with a second insulating layer. Afterward, opening a contact hole in the second insulating layer to the top of the small MTJ.

Abstract: A SOI DRAM unit comprising a MOS transistor and an improved SOI substrate having a back-gate control. The SOI substrate includes a first insulating layer, a first semiconductor layer having a first conductivity type, a second insulating layer, and a second semiconductor layer having a first conductivity type formed on a substrate. The MOS transistor includes a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second semiconductor layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively. A first oxidation region is formed in the first semiconductor layer below the source region and a second oxidation region is formed in the first semiconductor layer below the drain region. Both the first oxidation and second oxidation regions are contiguous with the second insulating layer.

Abstract: A method of fabricating a split gate flash memory cell is provided in the present invention. Firstly, a cap layer is formed on the surface of a silicon base of the semiconductor wafer. The surface of the silicon base is then etched to form at least one shallow trench. The shallow trench comprises a vertical sidewall composed of a protion of the silicon base. Next, an ion implantation process is performed using the cap layer to as a mask in order to form a doped area in both the bottom surface of the shallow trench and the silicon base beneath the cap layer. The doped area functions as a source. A first dielectric layer, floating gate, second dielectric layer, and a control gate are formed, respectively, the width of the floating gate being shorter than the width of the first dielectric layer. Then, a third dielectric layer is formed on the control gate and the cap layer is removed.

Abstract: A method for manufacturing a semiconductor device with a shallow channel on a silicon-on-insulator substrate is disclosed. The method uses a dielectric layer as a mask, an oxygen implantation and a heating process to form a silicon dioxide layer within a silicon-on-insulator substrate before forming a gate electrode on the silicon-on-insulator substrate. That is, the junction depth of the channel is reduced. First of all, a silicon-on-insulator substrate having a silicon layer and an insulating layer is provided, wherein the silicon layer is separated by the insulating layer. Secondly, a first dielectric layer is deposited on the silicon layer. Thirdly, a gate region pattern is transferred into the first dielectric layer to form a trench and expose the silicon layer. Then, oxygen molecules are implanted into the silicon layer, and the silicon-on-insulator substrate is heated to form a silicon dioxide layer therein. Next, a second dielectric layer is deposited and the trench is filled with the same.

Abstract: The present invention provides a method of making a dynamic random access memory (DRAM) unit. The method begins by providing a silicon-on-insulator substrate (SOI), the SOI substrate comprising a first isolation layer formed on a substrate, and a first silicon layer of a first conductive type formed on the first isolation layer. An oxygen ion implantation process is then performed to form a second isolation layer within the first silicon layer, the second isolation layer dividing the first silicon layer into an upper and a lower layer, or a second and a third silicon layer, respectively. Next, a shallow trench isolation is formed in the second silicon layer, as well as an active area isolated by the shallow trench isolation with the second isolation layer on the second silicon layer. Finally, a metal-oxide-semiconductor field-effect-transistor (MOSFET) is formed in the active area in the second silicon layer.

Abstract: A SOI DRAM unit comprising a MOS transistor and an improved SOI substrate having a back-gate control. The SOI substrate includes a first insulating layer, a first semiconductor layer having a first conductivity type, a second insulating layer, and a second semiconductor layer having a first conductivity type formed on a substrate, respectively. The MOS transistor includes a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second semiconductor layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively. A first doped region having a second conductivity type is formed in the first semiconductor layer below the source region and a second doped region having a second conductivity type is formed in the first semiconductor layer below the drain region. Both the first doped region and the second doped region are contiguous with the second insulating layer.

Abstract: A SOI DRAM unit comprising a MOS transistor and an improved SOI substrate having a back-gate control. The SOI substrate includes a first insulating layer, a first semiconductor layer having a first conductivity type, a second insulating layer, and a second semiconductor layer having a first conductivity type formed on a substrate. The MOS transistor includes a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second semiconductor layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively. A first oxidation region is formed in the first semiconductor layer below the source region and a second oxidation region is formed in the first semiconductor layer below the drain region. Both the first oxidation and second oxidation regions are contiguous with the second insulating layer.