Abstract: A SOI DRAM unit comprising a MOS transistor and an improved SOI substrate having a back-gate control. The SOI substrate includes a first insulating layer, a first semiconductor layer having a first conductivity type, a second insulating layer, and a second semiconductor layer having a first conductivity type formed on a substrate. The MOS transistor includes a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second semiconductor layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively. A first oxidation region is formed in the first semiconductor layer below the source region and a second oxidation region is formed in the first semiconductor layer below the drain region. Both the first oxidation and second oxidation regions are contiguous with the second insulating layer.

Abstract: The array includes: a plurality of pseudo spin valve (PSV) cells; a plurality of parallel bit lines, wherein a plurality of bit lines are straight lines and located under the plurality of pseudo spin valve (PSV) cells; a plurality of parallel word lines, wherein a plurality of word lines are continuous-bended lines having a first straight line, a second straight line and a third straight line. These straight lines of the word lines are orthogonal each other, wherein the first straight line and the third straight line are parallel. The first straight line and the third straight line are individually orthogonal with the direction of the bit lines. Furthermore, the second straight lines of the word lines are individually located on the pseudo spin valve (PSV) cells, and the second straight lines are parallel with the direction of the bit lines, so as to increase the magnetresistance ratio.

Abstract: A method of fabricating a buried vertical split gate memory cell is disclosed. First, a first trench is created in an SOI substrate for accommodating a floating gate. A second trench, having a smaller width than that of the first trench, is then created at the bottom of the first trench for accommodating a word line/control gate. Simultaneously, a silicon sidewall step structure is produced and functions as a vertical channel of the buried vertical split gate memory cell, wherein the vertical control gate channel length (LCG) and the floating gate channel length (LFG) is 0.25 micrometers and about 3.5 nm, respectively.

Abstract: The present invention relates to a method of forming a level silicon oxide layer on a semiconductor wafer. The semiconductor wafer comprises a substrate having a first region containing no silicon nitride on its surface and a second region which is higher than the first region and contains a silicon nitride layer on its surface. The method comprises performing a cleaning process on the semiconductor wafer with an alkaline solution to uniform the deposition rate over the surface of the first region; and performing a deposition process employing ozone as a reactive gas with a flow capacity of 80-200 g/L to form a silicon oxide layer above the first and second regions wherein the deposition rate of the silicon oxide layer on the first region is higher than that on the second region and the silicon oxide layer above the first region is leveled with that above the second region after a predetermined period of time.

Abstract: The invention relates to an ion implantation method for adjusting the threshold voltage of MOS transistors. The MOS transistor is employed in a DRAM (dynamic random access memory) memory cell in a semiconductor wafer and comprises a substrate, a gate insulating layer positioned on the substrate, and a gate conducting layer with a rectangular-shaped cross section positioned on the gate insulating layer. The method comprises performing an ion implantation process at a predetermined dosage and ion energy to implant dopants through the gate conducting layer and gate insulating layer and deposit the dopants into the superficial portion of the substrate below the gate insulating layer.

Abstract: The present invention provides a method of depositing a silicon oxide layer on a semiconductor wafer. The semiconductor wafer comprises a plurality of transistors positioned on its surface. The method comprises performing a cleaning process on the semiconductor wafer by using an alkaline solution to make a more uniform deposition rate of the silicon oxide layer on the transistors and other areas over the surface of the semiconductor wafer, then performing a deposition process by employing ozone as a reactive gas to form a silicon oxide layer of even thickness and without voids.

Abstract: The present invention provides a method of forming a contact hole in a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a silicon--oxygen layer positioned on the silicon substrate, and a photoresist layer positioned on the silicon--oxygen layer. An anisotropic dry-etching process is performed to vertically remove the silicon--oxygen layer below the opening to a predetermined depth to form the contact hole which contains a polymer layer on its surface. A soft-etching process is performed to remove the polymer layer in the contact hole. The dry-etching process and soft-etching process are performed alternatively to vertically remove the silicon--oxygen layer under the contact hole until the surface of the silicon substrate can be reached through the contact hole.