Abstract: A method for vehicle communication applied to a central gateway of a vehicle communication system. The method comprises: receiving zone information from a source zone controller of the plurality of zone controllers based on a time-sensitive network protocol, and the zone information comprises vehicle body data of a vehicle area controlled by the source zone controller; determining information to be transmitted based on the zone information; determining a target zone controller for receiving the information to be transmitted among the plurality of zone controllers based on the zone information; sending the information to be transmitted to the target zone controller based on the time-sensitive network protocol. A vehicle communication system, a central gateway, and a non-transitory storage medium are also provided.

Abstract: A probe card device includes a wiring board provided with a plurality of contacts, a probe head having a probe holder and a plurality of conductive probes arranged on the probe holder, respectively, and a circuit protection assembly including an insulation plate, a plurality of through holes and a plurality of self-resetting fusing elements. The insulation plate is sandwiched between the wiring board and the probe head. The through holes are respectively formed on the insulation plate and arranged in an array form. The self-resetting fusing elements are respectively disposed within the through holes. Each of the self-resetting fusing elements is electrically connected to one of the contacts and one of the conductive probes for reversibly breaking down electric currents from the wiring board to the conductive probe.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. The encapsulant laterally encapsulates the photonic die. The wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.

Abstract: An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal, and an array of write assist circuits coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell, and generate the output signal in response to a first control signal. The operating voltage corresponds to an output signal. Each write assist circuit includes an AND gate coupled to a programmable voltage tuner. The programmable voltage tuner includes a set of P-type transistors coupled to a first P-type transistor. The set of P-type transistors is coupled together in parallel, and receives a set of select control signals. A first terminal of the first P-type transistor is configured to receive an AND signal from the AND gate.

Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability.

Abstract: The disclosure provides a converter circuit, a power stage circuit and a temperature balancing method. The converter circuit includes power stage circuits and a control circuit. The power stage circuit includes a power circuit, a temperature sense circuit, a current sense circuit and a current feedback control circuit. The temperature sense circuit senses a temperature of the power stage circuit, to output a temperature sense value. The current sense circuit senses an output current of the power circuit, to output a current sense value. The current feedback control circuit compares the temperature sense value with a highest temperature value of the power stage circuits, and outputs one of the current sense value and adjusted current sense value to the control circuit according to a comparison result of the temperature sense value and the highest temperature value.

Abstract: Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. The third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. The dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer.

Abstract: A chip storing device includes a supporting frame, an elastic airbag and an airtight container. The supporting frame includes a loading tray having a receiving slot and a positioning portion. The receiving slot is used for containing a packaged chip. The positioning portion is disposed within the receiving slot, and used for limiting the elastic airbag. The airtight container is formed with an accommodating space therein. The supporting frame and the elastic air bag are completely received within the accommodation space. when the accommodation space is evacuated to be in a negative pressure environment, the volume of the elastic airbag is increased in the negative pressure environment, so that the elastic airbag that is inflated directly abuts against the packaged chip within the receiving slot.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: An element pickup mechanism includes a pick-up arm and an elastic gasket. The pick-up arm includes a bracket, an air-extraction pipe and a suction cup. The bracket is provided with an inner space and an opening that is formed on one side of the bracket and in communication with the inner space. The air-extraction pipe is disposed on the bracket and connected to a vacuum pump equipment. The suction cup is sleeved on one end of the air-extraction pipe, located in the inner space and faced towards the opening of the bracket. The elastic gasket includes a flexible pad and a through hole. The flexible pad is formed with a flat surface and an attached surface that is fixedly attached to the side of the bracket. The through hole penetrates through the flexible pad to coaxially align with the opening and the suction cup.

Abstract: An apparatus, system and method for storing die carriers and transferring a semiconductor die between the die carriers. A die stocker includes a rack enclosure with an integrated sorting system. The rack enclosure includes storage cells configured to receive and store die carriers having different physical configurations. A transport system transports first and second die carriers between a first plurality of storage cells and a first sorter load port, where the transport system introduces the first and second die carriers to a first sorter. The transport system transports third and fourth die carriers between a second plurality of storage cells and a second sorter load port, where the transport system introduces the third and fourth die carriers to a second sorter. The first and second die carriers have a first physical configuration, and the third and fourth die carriers have a second physical configuration, different than the first physical configuration.

Abstract: A tissue scaffold for use in a tendon and/or ligament is provided, which includes a weave formed by interlacing warp yarns and weft yarns, wherein the warp yarns include a plurality of fibers with an alternative shaped cross section structure, and the weave includes: a main body area with a bioactive component formed on the fiber surface, and a fixed area comprises the weft yarn having a bioceramic material. The tissue scaffold prepared in the present disclosure has the characteristics of stimulating the growth of tissues and inducing tissue repair, effectively improving the ability of tissue regeneration and bone healing, and is beneficial to the reconstruction of the tendon and/or ligament.

Abstract: A controller integrated circuit (IC) and a method for controlling a storage device for a host device to enhance overall performance are provided. The host device may include the controller IC, where the storage device is positioned outside the host device. The controller IC may include a plurality of first queues, a first queue notification register and a first queue auxiliary notification register, where each first queue of the first queues is arranged to queue first queue entries for being used to interact with the storage device. The first queue notification register may store first queue notification information for indicating whether any first queue of the plurality of first queues sends any first interrupt. The first queue auxiliary notification register may store first queue auxiliary notification information for indicating which first queue of the plurality of first queues is the any first queue that has sent the any first interrupt.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain portion adjacent to the gate electrode, and a semiconductor layer between the gate electrode and the source/drain portion.

Abstract: An idle time prediction method for a system includes obtaining n idle durations corresponding to n time points, determining if the n idle durations are of a normal distribution, generating a probability according to m idle states corresponding to m idle durations of the n idle durations if the n idle durations are not normally distributed, selecting a predicted idle state according to the probability, and controlling the system to enter the predicted idle state, where n and m are integers larger than one, and m?n.

Abstract: A memory erase method for a memory device and a memory device therefore are provided. The memory device is a 3D NAND flash with high capacity and high performance. The memory erase method includes following steps: providing a memory block, wherein the memory block comprises memory cell strings, the memory cell strings include memory cells, string selection transistors and ground selection transistors; respectively applying corresponding erase voltages to corresponding word lines, a common source line, a corresponding bit line, the string selection transistor and the ground selection transistor of each of the memory cell strings. The voltage difference between a bit line erase voltage and a string selection line erase voltage or the voltage difference between the common source line erase voltage and the ground selection line erase voltage is less than or equal to a predetermined voltage difference, and the memory cells of the memory cell strings randomly classified as a type-1 erase bit or a type-2 erase bit.

Abstract: A surface processing equipment using energy beam including a multi-axis platform, a surface profile measuring device, an energy beam generator and a computing device is provided. The multi-axis platform is configured to carry a workpiece and move the workpiece to the first position or the second position. The surface profile measuring device has a working area, and the first position is located on the working area. The surface profile measuring device is configured to measure the workpiece to obtain surface profile. The energy beam generator is configured to provide an energy beam to the workpiece for processing, and the second position is located on a transmission path of the energy beam. The computing device is connected to the surface profile measuring device and the energy beam generator. The computing device adjusts the energy beam generator according to the error profile.

Abstract: A locking mechanism for an aerosol drug delivery device includes a first housing, a second housing, a screw and a fastening member. The first housing has a contact portion and a fastening space formed beside the contact portion. The second housing is rotatably connected with the first housing and is capable of rotating relative to the first housing along a rotation axis. The screw is rotatably connected with the second housing and is capable of rotating relative to the second housing along a central axis parallel to the rotation axis. The fastening member is movably connected with the screw and capable of being driven by the screw to move toward the contact portion. The fastening member includes a fastening portion capable of being displaced when contacting with the contact portion and entering into the fastening space to limit the relative rotation between the first housing and the second housing.

Abstract: A method for use of exopolysaccharides of a lactic acid bacterium or a pharmaceutical composition containing the exopolysaccharides in the manufacture of a medicament for preventing, ameliorating and/or treating a sleeping disorder in a subject in need thereof.