Abstract: A system includes a host, a storage host controller, and a storage device. The host includes a hypervisor for running a first virtual machine and a second virtual machine. The storage host controller includes a plurality of first multi-circular queues (MCQs) assigned to the first virtual machine and a plurality of second MCQs assigned to the second virtual machine. The plurality of first MCQs assigned to the first virtual machine is used to control operations of the first virtual machine. The plurality of second MCQs assigned to the second virtual machine is used to control operations of the second virtual machine. The storage device has a first portion linked to the first virtual machine for being accessed by the first virtual machine, and a second portion linked to the second virtual machine for being accessed by the second virtual machine wherein the first portion and the second portion are isolated.

Abstract: A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. The encapsulant laterally encapsulates the photonic die. The wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.

Abstract: A host system operates to manage a storage device. The host system initiates an abort of a command when the command has been fetched from a submission queue (SQ) of the host system and the SQ entry has been fetched from the SQ and the host system has not received a corresponding command completion response from the storage device. The host system sends an abort request to the storage device, and issues a cleanup request to direct a host controller to reclaim host hardware resources allocated to the command. The host system adds a completion queue (CQ) entry to a CQ and sets an overall command status (OCS) value of the CQ entry to indicate completion of the abort request.

Abstract: Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.

Abstract: A trade fair positioning signal processing system and a method for using the positioning signal thereof are disclosed. The trade fair positioning signal processing system is used by a handheld mobile device of an attendee within a trade fair area, which includes a plurality of booths. The system includes a registration module, a management module, a plurality of positioning modules, a database, an analysis module, and an information dissemination module. The registration module provides attendee login. The management module calculates and generates a positioning data of the attendee, including a location and a residency time. The database is used to store the positioning information. When the analysis module determines that an attendee has stayed at a specific booth for more than a specific time, the information dissemination module is used to transmit a product introduction data belonging to the specific booth to the handheld mobile device.

Abstract: An object forming structure includes: at least two first original images, respectively provided with different vectors, and extended for forming at least two first original image three-dimensional shapes; at least one intersect fixed point, extended with at least one intersect direction through the intersect fixed point, wherein at least two second image three-dimensional shapes are formed through the first original image three-dimensional shapes being extended; and at least two third image three-dimensional shapes, stacked with the at least two second image three-dimensional shapes, wherein a Boolean function is utilized for confirming a selected desired zone for forming a new object formation; wherein, the new object formation formed via the third image three-dimensional shapes is obtained through a combination of intersect or union or equalize the different vectors, the first original image three-dimensional shapes are presented via the corresponding vectors for presenting different shapes in other angles.

Abstract: A surface processing equipment using energy beam including a multi-axis platform, a surface profile measuring device, an energy beam generator and a computing device is provided. The multi-axis platform is configured to carry a workpiece and move the workpiece to the first position or the second position. The surface profile measuring device has a working area, and the first position is located on the working area. The surface profile measuring device is configured to measure the workpiece to obtain surface profile. The energy beam generator is configured to provide an energy beam to the workpiece for processing, and the second position is located on a transmission path of the energy beam. The computing device is connected to the surface profile measuring device and the energy beam generator. The computing device adjusts the energy beam generator according to the error profile.

Abstract: A semiconductor device includes semiconductor nanostructures disposed over a substrate, and an electrical isolation region comprising a void disposed over the substrate in a drain/source region. The semiconductor device further includes a source/drain epitaxial layer in contact with the semiconductor nanostructures and disposed over the electrical isolation region in the drain/source region. The source/drain epitaxial layer is disposed over the void. The semiconductor device further includes a gate dielectric layer disposed on and wrapped around each channel region of the semiconductor nanostructures, and a gate electrode layer disposed on the gate dielectric layer and wrapped around each channel region of the semiconductor nanostructures.

Abstract: Semiconductor device includes light-emitting die and semiconductor package. Light emitting die includes substrate and first conductive pad. Substrate has emission region located at side surface. First conductive pad is located at bottom surface of substrate. Semiconductor package includes semiconductor-on-insulator substrate, interconnection structure, second conductive pad, and through semiconductor via. Semiconductor-on-insulator substrate has linear waveguide formed therein. Interconnection structure is disposed on semiconductor-on-insulator substrate. Edge coupler is embedded within interconnection structure and is connected to linear waveguide. Semiconductor-on-insulator substrate and interconnection structure include recess in which light-emitting die is disposed. Edge coupler is located close to sidewall of recess. Second conductive pad is located at bottom of recess. Through semiconductor via extends across semiconductor-on-insulator substrate to contact second conductive pad.

Abstract: A method according to the present disclosure includes providing a workpiece including a first fin-shaped structure and a second fin-shaped structure over a substrate, depositing a nitride liner over the substrate and sidewalls of the first fin-shaped structure and the second fin-shaped structure, forming an isolation feature over the nitride liner and between the first fin-shaped structure and the second fin-shaped structure, epitaxially growing a cap layer on exposed surfaces of the first fin-shaped structure and the second fin-shaped structure and above the nitride liner, crystalizing the cap layer, and forming a first source/drain feature over a first source/drain region of the first fin-shaped structure and a second source/drain feature over a second source/drain region of the second fin-shaped structure.

Abstract: A planar separation component for gas chromatograph includes a substrate made of aluminum, a porous anodic aluminum oxide separation member, and a cover unit. The substrate has a planar body, and a first flow channel having a first inlet and a first outlet. The separation member is formed on the substrate, and has a channel-defining wall defining the first flow channel and a plurality of nanosized pores in spatial communication with the first flow channel. The cover unit is bonded to the planar body for covering the first flow channel. Methods for manufacturing the planar separation component and separating a mixture containing compounds different in boiling point using the planar separation component are also disclosed.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. The third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. The dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer.

Abstract: A semiconductor structure includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a second conductive layer arranged within the dielectric layer and electrically connected to the first conductive layer, the second conductive layer including a sidewall distant from the dielectric layer by a width; and a first blocking layer over a surface of the first conductive layer between the second conducive layer and the dielectric layer. The first blocking layer includes at least one element of a precipitant.

Abstract: A testing apparatus includes a circuit board, a probe station and a probe array. The circuit board includes a plurality of contacts. The probe station includes a platform located on the circuit board and used for carrying a device under test (DUT), and a plurality of probe holes formed on the platform and arranged in an array. The probe array includes a plurality of telescopic probes respectively linearly inserted into the probe holes. One end of each of the telescopic probes is contacted with one of the contacts, and the other end thereof is contacted with one of solder balls of the DUT. Each of the probe holes includes an elongated groove penetrating through the platform. Each of the telescopic probes is provided with a fin protruding outwardly and inserting into the elongated groove.

Abstract: An information processing method controls a CT scanner such that the method includes, but is not limited to, determining an X-ray irradiation period from an electrocardiogram acquired from an electrocardiography device attached to a living object to be imaged, by processing the electrocardiogram at multiple different cardiac phases; performing, by controlling a CT gantry including and rotatably supporting an X-ray source and an X-ray detector, a diagnostic CT scan in the determined X-ray irradiation period, of at least a part of the heart region, to obtain a CT image; and causing a display unit to display the obtained CT image. The method can be performed at least by an information processing apparatus including processing circuitry and/or computer instructions stored in a non-transitory computer readable storage medium for performing the method.

Abstract: The present disclosure provides embodiments of semiconductor devices. In one embodiment, the semiconductor device includes a dielectric layer and a fin-shaped structure disposed over the dielectric layer. The fin-shaped structure includes a first p-type doped region, a second p-type doped region, and a third p-type doped region, and a first n-type doped region, a second n-type doped region, and a third n-type doped region interleaving the first p-type doped region, the second p-type doped region, and the third p-type doped region. The first p-type doped region, the third p-type doped region and the third n-type doped region are electrically coupled to a first potential. The second p-type doped region, the first n-type doped region and the second n-type doped region are electrically coupled to a second potential different from the first potential.

Abstract: An electronic device having a first area and a second area adjacent to the first area is provided, which includes a flexible substrate, a first conductive layer disposed on the flexible substrate and in the first area and the second area, a semiconductor disposed on the flexible substrate and electrically connected to the first conductive layer, a second conductive layer disposed on the first conductive layer, and an organic layer disposed on the first conductive layer and in the first area and the second area. The second conductive layer has a first portion and a second portion are respectively contacted the first conductive layer in the first area. In a cross-sectional view, a first portion of the organic layer is directly contacted the first conductive layer and the second conductive layer and disposed between the first portion and the second portion of the second conductive layer.

Abstract: A memory access latency estimation method includes measuring a first access latency of a first access operation of a first memory, measuring a plurality of first indexes of the first memory corresponding to the first access operation, using a plurality of first coefficients and the plurality of first indexes to perform a first weighted calculation to generate a first estimated latency, adjusting the plurality of first coefficients to generate a plurality of updated first coefficients, using the plurality of updated first coefficients and the plurality of first indexes to perform the first weighted calculation to adjust the first estimated latency for the first estimated latency to approximate the first access latency, and using the plurality of updated first coefficients and a plurality of second indexes of the first memory to perform a second weighted calculation to generate a second estimated latency for a second access operation.

Abstract: A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.