Abstract: An electronic device having a peripheral area and a non-peripheral area adjacent to the peripheral area is provided. The electronic device includes a flexible substrate, a first conductive layer disposed on the flexible substrate and disposed in the peripheral area and the non-peripheral area, an organic layer disposed in the non-peripheral area and on the first conductive layer, a second conductive layer disposed on the first conductive layer, and an organic structure disposed between the first conductive layer and the second conductive layer in the peripheral area. The organic layer and the organic structure are the same material layer.

Abstract: A flexible display module includes a first light-transmissive layer and a first display layer. The first light-transmissive layer includes a display surface. The first light-transmissive layer has a first width in a second direction. The first display layer is disposed below the first light-transmissive layer. The first display layer has a second width in the second direction. The first display layer includes a circuit layer. The flexible display module is configured to be bent along an axis, the axis extends along a first direction, the first direction is perpendicular to the second direction, and the first width is greater than the second width. A line width of the circuit layer more close to a periphery of the display surface is less than a line width of the circuit layer more close to an inner area of the display surface.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate and an epitaxial stack disposed above the semiconductor substrate. The epitaxial stack includes first and second type epitaxial layers, the first and second type epitaxial layers having different material compositions. The first and second type epitaxial layers are alternatingly disposed in a vertical direction. The semiconductor device also includes a first doped region in the epitaxial stack and a second doped region in the epitaxial stack. The first doped region has a first dopant of a first conductivity type. The second doped region has a second dopant of a second conductivity type opposite the first conductivity type. The semiconductor device also includes first and second gate stacks disposed above the epitaxial stack. A portion of the first doped region and a portion of the second doped region are between the first and second gate stacks.

Abstract: A monitor wafer is provided. The monitor wafer includes a substrate and a cleaning layer. The cleaning layer is disposed on a bottom surface of the substrate. The cleaning layer is configured to remove particles from the substrate and/or a processing tool.

Abstract: A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.

Abstract: A controller integrated circuit (IC) and a method for controlling a storage device for a host device to enhance overall performance are provided. The host device may include the controller IC, where the storage device is positioned outside the host device. The controller IC may include a plurality of first queues, a first queue notification register and a first queue auxiliary notification register, where each first queue of the first queues is arranged to queue first queue entries for being used to interact with the storage device. The first queue notification register may store first queue notification information for indicating whether any first queue of the plurality of first queues sends any first interrupt. The first queue auxiliary notification register may store first queue auxiliary notification information for indicating which first queue of the plurality of first queues is the any first queue that has sent the any first interrupt.

Abstract: A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.

Abstract: A testing apparatus includes a circuit board, a probe station and a probe array. The circuit board includes a plurality of contacts. The probe station includes a platform located on the circuit board and used for carrying a device under test (DUT), and a plurality of probe holes formed on the platform and arranged in an array. The probe array includes a plurality of telescopic probes respectively linearly inserted into the probe holes. One end of each of the telescopic probes is contacted with one of the contacts, and the other end thereof is contacted with one of solder balls of the DUT. Each of the probe holes includes an elongated groove penetrating through the platform. Each of the telescopic probes is provided with a fin protruding outwardly and inserting into the elongated groove.

Abstract: An impedance transformation circuit and a radio frequency power reliability test system are provided. The impedance transformation circuit can be used in a radio frequency power measurement system. The radio frequency power measurement system includes a signal generator, a buffer, a device under test, an attenuator, and a spectrum analyzer. The impedance transformation circuit includes a plurality of impedance transformers, which correspond to a plurality of impedance points on a reflection coefficient circle of a Smith chart, respectively. The impedance transformers are coupled between the device under test and the attenuator in turn in a radio frequency power reliability test, and the spectrum analyzer is configured to measure an output power corresponding to each of the impedance points, such that two of the impedance points respectively corresponding to a maximum output power and a minimum output power are found by the radio frequency power measurement system.

Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a material layer formed over the fin structure. The material layer and the isolation structure are made of different materials, the material layer has a top surface with a top width and a bottom surface with a bottom width, and the bottom width is greater than the top width.

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Abstract: A host system operates to manage a storage device. The host system initiates an abort of a command when the command has been fetched from a submission queue (SQ) of the host system and the SQ entry has been fetched from the SQ and the host system has not received a corresponding command completion response from the storage device. The host system sends an abort request to the storage device, and issues a cleanup request to direct a host controller to reclaim host hardware resources allocated to the command. The host system adds a completion queue (CQ) entry to a CQ and sets an overall command status (OCS) value of the CQ entry to indicate completion of the abort request.

Abstract: The invention encompasses hydrogels, monomer precursors of the hydrogels, methods for the preparation thereof, and methods of use therefor. The linking of monomers can take place using non-radical, bioorthogonal reactions such as copper-free click-chemistry.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: An embodiment of the invention provides a data transmission device. The data transmission device includes a first bus master control circuit, a second bus master control circuit, a storage circuit, a first control circuit and a second control circuit. The first bus master control circuit processes data transmissions associated with a peripheral device. The second bus master control circuit processes data transmissions associated with a system memory. The storage circuit stores information and instructions for data transmission. The first control circuit controls the first bus master control circuit according to the information and the instructions. The second control circuit controls the second bus master control circuit according to the information and the instructions.

Abstract: The purpose of the present invention is to provide a method for calculating a VC dimension boundary in a quantum circuit, the method comprising: a step in which a computer acquires the depth L of the quantum circuit; a step in which the computer acquires the width n of the quantum circuit; and a step in which the computer identifies the VC dimension boundary in the quantum circuit on the basis of the depth L and the width n.

Abstract: Disclosed is an anode material for a lithium-ion secondary battery, comprising: lithium titanate and a modified layer coating on the surface of the lithium titanate, wherein the modified layer is a fluorocarbon. The anode material forms a surface modification containing C—F bond on the surface of lithium oxide and can be used for the lithium electronic secondary battery, and the lithium electronic secondary battery comprises the anode material can avoid the formation of solid electrolyte layer on the surface of the electrode and obtain good conductivity and avoid gas production.

Abstract: Apparatus and methods are provided for thermal throttling for UE configured with multi-panel transceiving on FR2. In one novel aspect, the UE prioritizes throttling actions based on signal qualities of each transceiving panel. In one embodiment, the switching to the target panel from the active panel is selected as the highest priority throttling action when the signal quality of the target panel is similar to the active panel. In another embodiment, the UE further determines if the quality of the target panel is sufficient to support mmW transceiving before switching to the target panel. In one embodiment, the UE reduces one or more antennae of an active panel when the signal quality difference between the active panel and the target panel is bigger than a predefined gap threshold.

Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.

Abstract: A liquid storage tank includes a housing, a piston located in the housing, a cover, an elastic element, and an outlet pipe. The cover is attached to the housing and has a support post extending toward the piston. The piston, the housing, and the cover define a tank chamber. The tank chamber is filled with cooling liquid. The elastic element is connected with the tank hosing and the piston. The elastic element is free from contact with the cooling liquid. The outlet pipe communicates with the tank chamber. An extension direction of an opening of the outlet pipe is not parallel to a direction of movement of the elastic element. When the cooling liquid is decreased, the piston compressed the tank chamber such that the elastic element is released. The tank chamber is continuously compressed by pairing the elastic element and the piston.