Patents by Inventor Chih-Chien Liu
Chih-Chien Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11954453Abstract: Systems and methods for natural language generation by an edge computing device are disclosed. In one embodiments, a method comprises: receiving, by an edge computing device, event data from an edge event; determining, by the edge computing device, that a network connection to a cloud server is not available; extracting, by the edge computing device, features of the event data; predicting, by a local neural network of the edge computing device, an action for the edge computing device to take based on the features of the event data, wherein the action is associated with a confidence level; and determining, by the edge computing device, whether the confidence level meets a predetermined threshold value.Type: GrantFiled: March 12, 2019Date of Patent: April 9, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Hsiung Liu, I-Chien Lin, Cheng-Fang Lin, Joey H. Y. Tseng
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Patent number: 11799012Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.Type: GrantFiled: September 4, 2020Date of Patent: October 24, 2023Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
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Patent number: 11340662Abstract: A portable electronic device including a first body, a second body, a hinge mechanism, a control unit, a sensor unit, a sterilization module, and a shielding module, is provided. The first body has a first inner surface. The second body has a second inner surface. The hinge mechanism is connected between the first body and the second body. The control unit is disposed in the first body or the second body. The sensor unit is disposed in the first body or the second body and coupled to the control unit. The sterilization module is disposed at the hinge mechanism and coupled to the control unit, the sterilization module is configured to generate light for sterilization and disinfection. The shielding module is disposed on the hinge mechanism and the shielding module can move relative to the hinge mechanism.Type: GrantFiled: March 5, 2021Date of Patent: May 24, 2022Assignee: COMPAL ELECTRONICS, INC.Inventors: Yi-Chun Lin, Ya-Hui Tseng, I-Kai Liu, Po-Ching Chiang, Chien-Lun Sun, Yen-Kang Chen, Jih-Houng Lee, Chih-Chien Liu
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Patent number: 11222784Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.Type: GrantFiled: March 27, 2020Date of Patent: January 11, 2022Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
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Publication number: 20210286412Abstract: A portable electronic device including a first body, a second body, a hinge mechanism, a control unit, a sensor unit, a sterilization module, and a shielding module, is provided. The first body has a first inner surface. The second body has a second inner surface. The hinge mechanism is connected between the first body and the second body. The control unit is disposed in the first body or the second body. The sensor unit is disposed in the first body or the second body and coupled to the control unit. The sterilization module is disposed at the hinge mechanism and coupled to the control unit, the sterilization module is configured to generate light for sterilization and disinfection. The shielding module is disposed on the hinge mechanism and the shielding module can move relative to the hinge mechanism.Type: ApplicationFiled: March 5, 2021Publication date: September 16, 2021Applicant: COMPAL ELECTRONICS, INC.Inventors: Yi-Chun Lin, Ya-Hui Tseng, I-Kai Liu, Po-Ching Chiang, Chien-Lun Sun, Yen-Kang Chen, Jih-Houng Lee, Chih-Chien Liu
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Patent number: 10923809Abstract: A communication apparatus, an electronic apparatus and an antenna adjustment method thereof are provided. The communication apparatus includes an antenna system, a tuning portion and a switch circuit. The antenna system includes at least two antenna units. The tuning portion is disposed between the at least two antenna units and includes at least two branch units. The switch circuit is coupled to the tuning portion. The switch circuit switches a conduction from a first one of the branch units to a second one of the branch units according to a switching signal. The switching signal is related to performances of the antenna system. Accordingly, a dynamic and flexible adjustment mechanism can be provided to increase throughput and improve users' internet experience.Type: GrantFiled: April 2, 2019Date of Patent: February 16, 2021Assignee: COMPAL ELECTRONICS, INC.Inventors: Liang-Che Chou, Li-Chun Lee, Yu-Chun Hsieh, Mau-Chi Sun, Jui-Hung Lai, Wen-Feng Tsai, Chih-Chien Liu
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Publication number: 20200403077Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.Type: ApplicationFiled: September 4, 2020Publication date: December 24, 2020Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
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Patent number: 10804365Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.Type: GrantFiled: May 22, 2018Date of Patent: October 13, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
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Patent number: 10790289Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.Type: GrantFiled: September 26, 2019Date of Patent: September 29, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chih-Chien Liu, Tzu-Chin Wu, Po-Chun Chen, Chia-Lung Chang
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Patent number: 10770464Abstract: A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.Type: GrantFiled: February 14, 2018Date of Patent: September 8, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chih-Chien Liu, Chia-Lung Chang, Tzu-Chin Wu, Wei-Lun Hsu
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Publication number: 20200227264Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
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Patent number: 10651040Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.Type: GrantFiled: May 22, 2018Date of Patent: May 12, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
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Patent number: 10636794Abstract: A magnetic tunnel junction (MTJ) structure of a magnetic random access memory (MRAM) cell includes an insulation layer, a patterned MTJ film stack, an aluminum oxide protection layer, an interlayer dielectric, and a connection structure. The patterned MTJ film stack is disposed on the insulation layer. The aluminum oxide protection layer is disposed on a sidewall of the patterned MTJ film stack, and the aluminum oxide protection layer includes an aluminum film oxidized by an oxidation treatment. The interlayer dielectric covers the aluminum oxide protection layer and the patterned MTJ film stack. The connection structure penetrates the interlayer dielectric above the patterned MTJ film stack, and the connection structure is electrically connected to a topmost portion of the patterned MTJ film stack.Type: GrantFiled: May 2, 2019Date of Patent: April 28, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsiao-Pang Chou, Yu-Ru Yang, Chih-Chien Liu, Chao-Ching Hsieh, Chun-Hsien Lin
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Publication number: 20200020693Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.Type: ApplicationFiled: September 26, 2019Publication date: January 16, 2020Inventors: Chih-Chien Liu, Tzu-Chin Wu, Po-Chun Chen, Chia-Lung Chang
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Patent number: 10497705Abstract: The present invention provides a bit line gate structure comprising a substrate, an amorphous silicon layer disposed on the substrate, a first doped region located in the amorphous silicon layer, a titanium silicon nitride (TiSiN) layer, located in the amorphous silicon layer, and a second doped region located in the TiSiN layer, the first doped region contacts the second doped region directly.Type: GrantFiled: May 6, 2018Date of Patent: December 3, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Pin-Hong Chen, Yi-Wei Chen, Chun-Chieh Chiu, Chih-Chieh Tsai, Tzu-Chieh Chen, Chih-Chien Liu
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Patent number: 10465287Abstract: A semiconductor device includes a substrate, a dielectric layer, a first tungsten layer, an interface layer and a second tungsten layer. The dielectric layer is disposed on the substrate and has a first opening and a second opening larger than the first opening. The first tungsten layer is filled in the first opening and is disposed in the second opening. The second tungsten layer is disposed on the first tungsten layer in the second opening, wherein the second tungsten layer has a grain size gradually increased from a bottom surface to a top surface. The interface layer is disposed between the first tungsten layer and the second tungsten layer, wherein the interface layer comprises a nitrogen containing layer. The present invention further includes a method of forming a semiconductor device.Type: GrantFiled: March 12, 2018Date of Patent: November 5, 2019Assignees: UNITED MICROELECTRONCIS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chih-Chien Liu, Pin-Hong Chen, Tsun-Min Cheng, Yi-Wei Chen
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Patent number: 10468417Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.Type: GrantFiled: April 23, 2018Date of Patent: November 5, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chih-Chien Liu, Tzu-Chin Wu, Po-Chun Chen, Chia-Lung Chang
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Publication number: 20190318933Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.Type: ApplicationFiled: May 22, 2018Publication date: October 17, 2019Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
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Publication number: 20190319107Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.Type: ApplicationFiled: May 22, 2018Publication date: October 17, 2019Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
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Publication number: 20190319031Abstract: The present invention provides a bit line gate structure comprising a substrate, an amorphous silicon layer disposed on the substrate, a first doped region located in the amorphous silicon layer, a titanium silicon nitride (TiSiN) layer, located in the amorphous silicon layer, and a second doped region located in the TiSiN layer, the first doped region contacts the second doped region directly.Type: ApplicationFiled: May 6, 2018Publication date: October 17, 2019Inventors: Pin-Hong Chen, Yi-Wei Chen, Chun-Chieh Chiu, Chih-Chieh Tsai, Tzu-Chieh Chen, Chih-Chien Liu