Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.

Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.

Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.

Abstract: A method for forming a FinFET structure includes providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively. A first oxide layer cover the first fin structure and the second fin structure. Next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, and the first protective layer within the first region is then removed. Afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.

Abstract: A computer booting method is provided for a computer system. The method comprises performing a power-on-self test. When the test result shows no error on the BIOS, a booting procedure is executed. When the test result shows the BIOS is damaged, whether the computer system stores a backup file of the BIOS is determined. When the computer system stores the backup file, the central processing unit reads the data of backup file and write it into a BIOS system memory and a reboot process is performed. When there is no backup file in the computer system, the computer system is connected to an internet server and downloads a BIOS backup file to the system main memory from the internet server. The central processing unit reads the BIOS backup file and write it into the BIOS system memory and a reboot process is formed.

Abstract: A transistor includes a semiconductor substrate, at least a gate structure, at least a first tensile stress layer, a second tensile stress layer, a source region, and a drain region. The gate structure is disposed within a first transistor region of the semiconductor substrate. The first tensile stress layer includes a curved portion encompassing the gate structure, at least an extension portion with a curved top surface located on the semiconductor substrate at sides of the gate structure, and a transition portion between the curved portion and the extension portion. The first tensile stress layer has a thickness gradually thinning from the curved portion and the extension portion toward the transition portion. The second tensile stress layer is disposed on the first tensile stress layer. And the source/drain regions are separately located in the semiconductor substrate on two sides of the gate structure.

Abstract: A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma.

Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a metal-oxide semiconductor (MOS) transistor disposed in the substrate; and a shallow trench isolation (STI) disposed in the substrate and around the MOS transistor, in which the STI comprises a stress material.

Abstract: A method of fabricating semiconductor patterns includes steps as follows: Firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed. Then, a surface portion of the second semiconductor pattern is reacted to form a sacrificial structure layer. Then, the barrier pattern and the sacrificial structure layer are removed, and the line width of the second semiconductor pattern is shrunken to be less than the line width of the first semiconductor pattern. A third semiconductor pattern having a line width can be further provided.

Abstract: A semiconductor structure includes a fin-shaped structure and a gate. The fin-shaped structure is located in a substrate, wherein the fin-shaped structure has a through hole located right below a vacant part. The gate surrounds the vacant part. Moreover, the present invention also provides a semiconductor process including the following steps for forming said semiconductor structure. A substrate is provided. A fin-shaped structure is formed in the substrate, wherein the fin-shaped structure has a bottom part and a top part. A part of the bottom part is removed to form a vacant part in the corresponding top part, thereby forming the vacant part over a through hole. A gate is formed to surround the vacant part.

Abstract: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height.

Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

Abstract: A fin field-effect transistor structure comprises a substrate, a fin channel, a source/drain region, a high-k metal gate and a plurality of slot contact structures. The fin channel is formed on the substrate. The source/drain region is formed in the fin channel. The high-k metal gate formed on the substrate and the fin channel comprises a high-k dielectric layer and a metal gate layer, wherein the high-k dielectric layer is arranged between the metal gate layer and the fin channel. The slot contact structures are disposed at both sides of the metal gate.

Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.

Abstract: A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.

Abstract: A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor.

Abstract: An ALD method includes providing a substrate in an ALD reactor, performing a pre-ALD treatment to the substrate in the ALD reactor, and performing one or more ALD cycles to form a dielectric layer on the substrate in the ALD reactor. The pre-ALD treatment includes providing a hydroxylating agent to the substrate in a first duration, and providing a precursor to the substrate in a second duration. Each of the ALD cycles includes providing the hydroxylating agent to the substrate in a third duration, and providing the precursor to the substrate in a fourth duration. The first duration is longer than the third duration.

Abstract: A method for forming an isolation structure includes the following steps. A hard mask layer is formed on a substrate and a trench is formed in the substrate and the hard mask layer. A protective layer is formed to cover the trench and the hard mask layer. A first isolation material is filled into the trench. An etching process is performed to etch back part of the first isolation material.

Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.