Abstract: A semiconductor device with fin-shaped structure is disclosed. The semiconductor device includes: a substrate; a fin-shaped structure on the substrate; and an epitaxial layer on a top surface and part of the sidewall of the fin-shaped structure, in which the epitaxial layer and the fin-shaped structure includes a linear gradient of germanium concentration therebetween.

Abstract: An operating method of an electronic apparatus and a touch apparatus are provided. In the method, a touch action by a user on a touch panel is detected through a controller of the touch apparatus, so as to obtain a contact region touched by the touch action on the touch panel. Subsequently, whether the touch action includes a palm touch is determined based on a size of the contact region. Under the situation that the touch action includes the palm touch, palm touching information corresponding to the palm touch is transformed into mouse controlling information through a mouse simulating device of the touch apparatus. Further, the mouse controlling information is sent to a mouse driver through the mouse simulating device, such that the mouse driver executes mouse operation based on the mouse controlling information.

Abstract: A gap-filling dielectric layer, method for fabricating the same and applications thereof are disclosed. A silicon-containing dielectric layer is firstly deposited on a substrate. The silicon-containing dielectric layer is then subjected to a curing process, an in-situ wetting treatment and an annealing process in sequence, whereby a gap-filling dielectric layer with a nitrogen atom density less than 1×1022 atoms/cm3 is formed.

Abstract: A via structure and a method of forming the same are provided. In the forming method of the present invention, a via is formed in a dielectric layer. Next, a U-shaped seed layer is formed in the via. After that, a conductive material is selectively formed in the via to form a conductive bulk layer in the via. Through the present invention, the purposes of effectively removing the overhang adjacent to the opening of the via and protecting the U-shaped seed layer in the via can be achieved.

Abstract: A semiconductor device with fin-shaped structure is disclosed. The semiconductor device includes: a substrate; a fin-shaped structure on the substrate; and an epitaxial layer on a top surface and part of the sidewall of the fin-shaped structure, in which the epitaxial layer and the fin-shaped structure includes a linear gradient of germanium concentration therebetween.

Abstract: A management method of a hybrid storage unit and an electronic apparatus of the hybrid storage unit are provided. The electronic apparatus includes a hybrid storage unit. The hybrid storage unit includes a first storage unit and a second storage unit. The second storage unit includes a first storage area and a second storage area. If a relationship between the electronic apparatus and an external apparatus is detected as being an undocked relationship, the first storage unit is disabled by a controller of the hybrid storage unit, and the second storage area serves to simulate and replace the first storage unit. The controller reports a storage unit status change notification to an operating system, so as to allow the operating system to re-enumerate the hybrid storage unit.

Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating deposition are substantially aligned with the top surface of the insulation.

Abstract: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height.

Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.

Abstract: A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.

Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.

Abstract: A computer system and a bootup and shutdown method thereof are provided. The computer system includes a memory, a chipset, a basic input/output system (BIOS), and an embedded controller, and an operating system (OS) is executed in the computer system. In the shutdown and bootup method, the embedded controller is notified to prepare to enter into a standby mode when the BIOS intercepts a shutdown instruction issued by the OS. The content of a register of the chipset is set according to the standby mode. A current operation mode data of the computer system is retained, and power is continuously supplied to the memory to make the computer system enter into the standby mode.

Abstract: A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps. A substrate with a plurality of dummy gate structures formed thereon and a first dielectric layer covering the dummy gate structures is provided, the dummy gate structures comprising a plurality of dummy gates and a plurality of insulating layers formed on the dummy gates, wherein at least two of the dummy gate structures have different heights. A first planarization process is performed to expose at least one of the dummy gate structures having the highest height. A first etching process is performed to expose the insulating layers. A chemical mechanical polishing (CMP) process with a non-selectivity slurry is performed to planarize the dummy gate structures. The planarized dummy gate structures are removed to form a plurality of gate trenches.

Abstract: A method for switching operating systems and an electronic apparatus are provided. A first operating system (OS) is notified to enter a power saving mode when a switching signal is received in case of running the first OS. In the power saving mode, a first running data of the first OS is stored to a first dump area of a storage unit from a system memory, a second OS is loaded to the system memory such that the second OS enters a normal operating mode.

Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.

Abstract: A method for forming a FinFET structure includes providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively. A first oxide layer cover the first fin structure and the second fin structure. Next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, and the first protective layer within the first region is then removed. Afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.

Abstract: A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.) . Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer.