Patents by Inventor Chih-Chien Liu

Chih-Chien Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10269868
    Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a fin transistor (fin filed effect transistor, finFET) located on a substrate, the fin transistor includes a gate structure crossing over a fin structure, and at least one source/drain region. And a resistive random access memory (RRAM) includes a lower electrode, a resistance switching layer and a top electrode being sequentially located on the source/drain region and electrically connected to the fin transistor.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 23, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ru Yang, Chih-Chien Liu, Chao-Ching Hsieh, Hsiao-Pang Chou
  • Publication number: 20190115394
    Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate comprising a diffusion region, a transistor structure on the substrate, and a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory includes at least one metal silicide layer in direct contact with the diffusion region, and a lower electrode, a resistive switching layer and an upper electrode are sequentially disposed on the metal silicide layer.
    Type: Application
    Filed: November 8, 2017
    Publication date: April 18, 2019
    Inventors: Chih-Chien Liu, Chao-Ching Hsieh, Yu-Ru Yang, Hsiao-Pang Chou
  • Patent number: 10177311
    Abstract: A resistive random access memory (RRAM) cell includes a substrate, a transistor having a gate on the substrate and a source/drain region in the substrate, a first inter-layer dielectric layer covering the transistor, a contact plug disposed in the first inter-layer dielectric layer and landing on the source/drain region, a resistive material layer conformally covering a protruding upper end portion of the contact plug, and a top electrode on the resistive material layer.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: January 8, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Ching Hsieh, Chih-Chien Liu, Yu-Ru Yang, Hsiao-Pang Chou
  • Patent number: 10141193
    Abstract: A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Publication number: 20180331044
    Abstract: A semiconductor device including a tungsten contact structure formed in a first dielectric layer on a substrate is provided. The tungsten contact structure contains a seam structure. A tungsten oxide layer is formed at least on a sidewall of the seam structure.
    Type: Application
    Filed: June 15, 2017
    Publication date: November 15, 2018
    Applicant: United Microelectronics Corp.
    Inventors: Yi-Yu Wu, Chun-Yuan Wu, Chih-Chien Liu, Bin-Siang Tsai
  • Patent number: 10089457
    Abstract: An application program is implemented by an electrical device for executing a wireless network certification process, which includes the following steps: driving a network module of the electrical device to receive a certification code broadcasted by a wireless network access point (AP), determining whether or not the certification code is in an identified list, wherein when the certification code is not in the identified list, the application program executes a first action to limit the electrical device to a limited function mode; and when an unlock password is received, the application program executing a second action to unlock the electrical device to an un-limited function mode; and when the electrical device is in the un-limited function mode and a connecting password is received, driving the network module of the electrical device to connect to the network AP.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: October 2, 2018
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Chih-Chien Liu, Yi-Chang Chen, Chih-Hsing Kang
  • Patent number: 10014227
    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: July 3, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chih-Chien Liu, Chin-Cheng Chien, Chin-Fu Lin
  • Patent number: 9971504
    Abstract: A management method of a hybrid storage unit and an electronic apparatus of the hybrid storage unit are provided. The electronic apparatus includes a hybrid storage unit. The hybrid storage unit includes a first storage unit and a second storage unit. The second storage unit includes a first storage area and a second storage area. If a relationship between the electronic apparatus and an external apparatus is detected as being an undocked relationship, the first storage unit is disabled by a controller of the hybrid storage unit, and the second storage area serves to simulate and replace the first storage unit. The controller reports a storage unit status change notification to an operating system, so as to allow the operating system to re-enumerate the hybrid storage unit.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: May 15, 2018
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Chih-Chien Liu, Chun-Sheng Chen, Sheng-Hung Lee, Chin-Kuo Huang, Chin-Liang Hsu
  • Patent number: 9923095
    Abstract: The present invention provides a non-planar FET and a method of manufacturing the same. The non-planar FET includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: March 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Chia-Lin Hsu
  • Patent number: 9715267
    Abstract: A method for switching operating systems and an electronic apparatus are provided. A first operating system (OS) is notified to enter a power saving mode when a switching signal is received in case of running the first OS. In the power saving mode, a first running data of the first OS is stored to a first dump area of a storage unit from a system memory, a second OS is loaded to the system memory such that the second OS enters a normal operating mode.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 25, 2017
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Chih-Chien Liu, Chun-Sheng Chen
  • Patent number: 9673053
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: June 6, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Rung-Yuan Lee, Yu-Ting Li, Jing-Yin Jhang, Chen-Yi Weng, Jia-Feng Fang, Yi-Wei Chen, Wei-Jen Wu, Po-Cheng Huang, Fu-Shou Tsai, Kun-Ju Li, Wen-Chin Lin, Chih-Chien Liu, Chih-Hsun Lin, Chun-Yuan Wu
  • Publication number: 20170098710
    Abstract: The present invention provides a non-planar FET and a method of manufacturing the same. The non-planar FET includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Chia-Lin Hsu
  • Patent number: 9559189
    Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: January 31, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Chia-Lin Hsu
  • Patent number: 9461150
    Abstract: A method for fabricating semiconductor device with fin-shaped structure is disclosed. The method includes the steps of: forming a fin-shaped structure on a substrate; forming a first dielectric layer on the substrate and the fin-shaped structure; depositing a second dielectric layer on the first dielectric layer; etching back a portion of the second dielectric layer; removing part of the first dielectric layer to expose a top surface and part of the sidewall of the fin-shaped structure; forming an epitaxial layer to cover the exposed top surface and part of the sidewall of the fin-shaped structure; and removing a portion of the second dielectric layer.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: October 4, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Hsin-Kuo Hsu, Chih-Chien Liu, Chin-Fu Lin, Chun-Yuan Wu
  • Publication number: 20160226873
    Abstract: A non-transitory computer readable storage medium for storing an application program for network certification is disclosed. The application program is implemented by an electrical device for executing a wireless network certification process. The wireless network certification process includes the following steps: driving a network module of the electrical device to receive a certification code broadcasted by a wireless network access point (AP), determining if the certification code is in an identified list, executing an action to limit communication between the electrical device and the network AP when the certification code is not in the identified list, and receiving a password for removing the limitation of the communication.
    Type: Application
    Filed: April 13, 2016
    Publication date: August 4, 2016
    Inventors: Chih-Chien LIU, Yi-Chang CHEN, Chih-Hsing KANG
  • Patent number: 9401429
    Abstract: A semiconductor structure includes a fin-shaped structure and a gate. The fin-shaped structure is located in a substrate, wherein the fin-shaped structure has a through hole located right below a suspended part. The gate surrounds the suspended part. Moreover, the present invention also provides a semiconductor process including the following steps for forming said semiconductor structure. A substrate is provided. A fin-shaped structure is formed in the substrate, wherein the fin-shaped structure has a bottom part and a top part. A part of the bottom part is removed to form a suspended part in the corresponding top part, thereby forming the suspended part over a through hole. A gate is formed to surround the suspended part.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: July 26, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chia-Lin Hsu
  • Publication number: 20160211144
    Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.
    Type: Application
    Filed: February 25, 2015
    Publication date: July 21, 2016
    Inventors: Yu-Ying Lin, Ted Ming-Lang Guo, Chin-Cheng Chien, Chih-Chien Liu, Hsin-Kuo Hsu, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 9384996
    Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating depositions are substantially aligned with the top surface of the insulation.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: July 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Cheng Huang, Yu-Ting Li, Jen-Chieh Lin, Kun-Ju Li, Chang-Hung Kung, Yue-Han Wu, Chih-Chien Liu
  • Patent number: 9362358
    Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: June 7, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Hung-Lin Shih, Chih-Chien Liu, Jei-Ming Chen, Wen-Yi Teng, Chieh-Wen Lo
  • Publication number: 20160148816
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 26, 2016
    Inventors: Rung-Yuan Lee, Yu-Ting Li, Jing-Yin Jhang, Chen-Yi Weng, Jia-Feng Fang, Yi-Wei Chen, Wei-Jen Wu, Po-Cheng Huang, Fu-Shou Tsai, Kun-Ju Li, Wen-Chin Lin, Chih-Chien Liu, Chih-Hsun Lin, Chun-Yuan Wu