Abstract: A damascene process for forming a via that leads to a conductive layer on a substrate. A low dielectric constant material layer is formed over the substrate. A low temperature hard mask layer is formed over the low dielectric constant material layer. The low temperature hard mask layer is patterned to form an opening above the conductive layer. Using the low temperature hard mask layer as a mask, the exposed low dielectric constant material layer is etched to form a via hole. An adhesion promoter liner is formed on the interior walls of the via hole. Metallic material is deposited into the via hole to form a via.

Abstract: A method of manufacturing a metal-oxide-semiconductor field effect (MOSFET) device. A substrate having an isolating structure thereon is provided. A gate dielectric layer and a conductive layer are sequentially formed over the substrate. The conductive layer and the gate dielectric layer are patterned to form a gate structure. A low dielectric constant material spacer is formed on the sidewall of the gate structure. A source drain region is formed in the substrate on each side of the gate structure.

Abstract: A fabrication method for shallow trench isolation is provided. The method includes forming a pad oxide layer on a substrate, followed by forming a mask layer on the pad oxide layer. The mask layer is then patterned. Using the patterned mask as a mask, the pad oxide layer and the substrate are etched to form a trench in the substrate. A tilt-angled fluorine implantation is performed to form a substrate surface with fluorine ions around the top corner of the trench. A thermal oxidation process is further conducted on a surface of the trench to form a thicker liner oxide layer at the top corner of the trench. An insulation layer is then formed on the substrate, filling the trench. The insulation layer above the mask layer is removed followed by removing the mask layer and the pad oxide layer.

Abstract: A method of manufacturing a metal-oxide-semiconductor field effect (MOSFET) device. A substrate having an isolating structure thereon is provided. A gate dielectric layer and a conductive layer are sequentially formed over the substrate. The conductive layer and the gate dielectric layer are patterned to form a gate structure. A low dielectric constant material spacer is formed on the sidewall of the gate structure. A source drain region is formed in the substrate on each side of the gate structure.

Abstract: A method for forming a damascene opening in a polymer-based dielectric layer is introduced. The method includes providing a substrate, which has also a conductive structure layer and a polymer-based dielectric layer formed thereon already. The polymer-based dielectric layer is uniformly hardened by a thermal treatment. A mask layer is formed on the polymer-based dielectric layer. The mask layer and the polymer-based dielectric layer are patterned to form an opening. The opening exposes a surface of the polymer-based dielectric layer. The exposed surface of the polymer-based dielectric layer is further hardened by a local hardening process. The local hardening process includes using an irradiation source of a high energy light beam, electron beam or ion beam to proceed the local hardening. The irradiation source can be incident onto the substrate by vertical angle or inclining angle. The substrate can also be rotated.

Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.

Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.

Abstract: A method of forming a dual damascene structure. A first dielectric layer and a second dielectric layer are sequentially formed over a substrate. A first photoresist layer is formed over the second dielectric layer. Photolithographic and etching operations are conducted to remove a portion of the second dielectric layer and the first dielectric layer so that a via opening is formed. A conformal third dielectric layer is coated over the surface of the second dielectric layer and the interior surface of the via opening. The conformal third dielectric layer forms a liner dielectric layer. A second photoresist layer is formed over the second dielectric layer and then the second photoresist layer is patterned. Using the patterned second photoresist layer as a mask, a portion of the second dielectric layer is removed to form a trench. The patterned second photoresist layer is removed. Conductive material is deposited over the substrate to fill the via opening and the trench.

Abstract: A method is used to form an intermetal dielectric layer. According to the invention, an unbiased-unclamped fluorinated silicate glass layer used as a protection layer is formed by high density plasma chemical vapor deposition on a biased-clamped fluorinated silicate glass layer formed by high density plasma chemical vapor deposition to prevent the biased-clamped fluorinated silicate glass layer from being exposed in a planarization process.

Abstract: A method of filling a gap is proposed. The method of the invention is applied on a substrate which has conductive structures formed thereon. A HDPCVD is performed to form a dielectric layer on the substrate. The HDPCVD process comprises multi-steps. In a first step, a gas source is added to a deposition chamber to form dielectric material over the substrate. The gas source comprises reactive gas and inert gas. Thus, the first step can simultaneously perform deposition and sputtering. In a second step, the reactive gas is driven out of the deposition chamber. Only sputtering is used to remove a part of the dielectric material at top corners of the conductive structures. In a third step, the reactive gas is again added into the deposition chamber to deposit the dielectric material until filling the gap.

Abstract: A method for stripping a low dielectric film with a high carbon content from silicon monitor chip. The silicon monitor chip is placed inside a plasma-enhanced chemical vapor deposition chamber and the surface is treated with oxygen plasma to form a silicon-rich oxide layer. A high-carbon-content low dielectric film is formed over the silicon-rich oxide for film quality inspection. After the film inspection, the silicon monitor chip is immersed in a solution containing ammonium hydroxide and hydrogen peroxide so that the surface of the high-carbon-content dielectric film is transformed from hydrophobic to hydrophilic. Hence, wetting capacity of subsequently applied hydrofluoric acid solution is enhanced. Finally, the silicon monitor chip is immersed in a hydrofluoric acid solution for stripping away the low dielectric film.

Abstract: A fabrication method for an inter-metal dielectric layer is applicable to multi-level interconnects. A substrate is provided with metal lines formed thereon. A first (fluorinated silicon glass) FSG layer with low fluorine content is then formed on the substrate, followed by forming a biased-clamped FSG layer on the first FSG layer. A second FSG layer with low fluorine content is formed on the biased-clamped layer, prior to forming an oxide cap layer on the second FSG layer. The oxide cap layer is planarized until the oxide cap layer is level with the second FSG layer.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

Abstract: A method of forming an inter-metal interconnection is provided. A substrate is provided. A dielectric layer with a metal plug therein is formed on the substrate. An IMD layer is formed on the dielectric layer. An insulating layer and a PE-oxide layer are formed on the IMD layer. A photolithography and etching process is performed to form a trench in the IMD layer and to expose the metal plug in the dielectric layer. A metal is filled into the trench to electrically connect to the metal plug.

Abstract: A method of fabricating a copper capping layer. A silicon rich nitride layer is formed on an exposed copper layer. Since the silicon rich nitride layer has more dangling bonds inside, the silicon in the silicon rich nitride layer easily reacts with the copper and a copper silicide layer is formed between the copper and the silicon rich nitride layer. Therefore, adhesion of the copper and the silicon rich nitride layer can be improved.

Abstract: A barrier layer is formed over the substrate by deposition, and a first dielectric is formed over the diffusion barrier layer by deposition. A etching stop layer and a second dielectric are formed in turn over the first dielectric by deposition. Next, a hard mask is formed on the second dielectric. Then, a photoresist layer is formed over the hard mask, and defining the photoresist layer. And then dry etching is carried out by means of the photoresist layer as the mask to form a via hole. A gap-filling material is filled on the second dielectric and into the via hole by conventional partial-cured (or un-cured) spin-on glass method. A anti-reflection layer is formed over the second dielectric by deposition. Another photoresist layer is formed on the anti-reflection coating and defined the photoresist layer, and to expose the partial surface of the via hole and the anti-reflection coating.

Abstract: A method for fabricating dual damascene is to form an undoped silicate glass (USG) liner before forming a fluorinated silicate glass (FSG) layer which serves as an inter-metal dielectric (IMD) layer on a semiconductor substrate. As a result, the surface sensitivity is eliminated, while a FSG layer with a more uniform thickness and a higher reliability is obtained. In addition, the USG liner increases the adhesion between the FSG layer and other material layers, while no particles are easily formed thereon.

Abstract: A method for forming an inter-metal dielectric layer without voids therein is described. Wiring lines are formed on a provided substrate. Each of the wiring lines comprises a protective layer thereon. A liner layer is formed over the substrate and over the wiring lines. An FSG layer is formed on the liner layer by using HDPCVD. A thickness of the FSG layer is about 0.9-1 times a thickness of the wiring lines. A cap layer is formed on the FSG layer using HDPCVD. A thickness of the cap layer is about 0.2-0.3 times a thickness of the wiring lines. An oxide layer is formed on the cap layer to achieve a predetermined thickness. A part of the dielectric layer is removed to obtain a planarized surface.

Abstract: The present invention relates to a method for preventing an electrostatic chuck positioned at the bottom of a plasma vacuum chamber from being corroded during a cleaning process. The electrostatic chuck comprises a conductive substrate functioned as a lower electrode in a plasma process, and an insulating layer on the conductive substrate to electrically isolate the semiconductor wafer and the conductive substrate. The cleaning process involves a plasma process in which a fluorine-contained gas is injected into the plasma vacuum chamber to remove the chemical layer on the inner wall of the plasma vacuum chamber. A ceramic shutter made of SiC material is reposed on the electrostatic chuck and a high DC voltage is applied to the conductive substrate and the ceramic shutter which causes the ceramic shutter and the electrostatic chuck tightly stick together due to an electrostatic reaction.

Abstract: A method of fabricating a shallow trench isolation structure is described. A preserve layer is formed on a substrate. A trench is formed in the substrate and the preserve layer. An oxide layer is formed over the substrate to fill the trench. A wet densification step is performed in a moist environment. A planarization step is performed until the preserve layer is exposed. A shallow trench isolation structure is formed.