Patents by Inventor Chih-Chien Liu

Chih-Chien Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing semiconductor device with silicide
    Patent number: 8476164
    Abstract: A method of manufacturing semiconductor device is provided. A substrate at least with a patterned silicon-containing layer on the substrate and spacers adjacent to the patterned silicon-containing layer is provided. A metal layer is formed on the substrate and covers the patterned silicon-containing layer and spacers. Then, a capping layer is formed on the metal layer. A first rapid thermal process is performed to at least make a portion of the metal layer react with the substrate around the spacers to form transitional silicides. The capping layer and the unreacted portions of the metal layer are removed. A first nitride film with a first tensile stress S1 is formed on the substrate. A second rapid thermal process is performed to transfer the transitional silicide to a silicide and transfer the first nitride film to a second nitride film with a second tensile stress S2, wherein S2>S1.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: July 2, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Fu Lin, Chin-Cheng Chien, Chih-Chien Liu, Chia-Lin Hsu, Chun-Yuan Wu
  • Non-planar semiconductor structure and fabrication method thereof
    Patent number: 8441072
    Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: May 14, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shih-Hung Tsai, Chien-Ting Lin, Chin-Cheng Chien, Chin-Fu Lin, Chih-Chien Liu, Teng-Chun Tsai, Chun-Yuan Wu
  • Method for fabricating semiconductor device
    Patent number: 8431473
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer comprises metal interconnects therein; forming a top metal layer on the dielectric layer; and forming a passivation layer on the top metal layer through high-density plasma chemical vapor deposition (HDPCVD) process.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: April 30, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shu-Hui Hu, Shih-Feng Su, Hui-Shen Shih, Chih-Chien Liu, Po-Chun Chen, Ya-Jyuan Hung, Bin-Siang Tsai, Chin-Fu Lin
  • SEMICONDUCTOR PROCESS
    Publication number: 20130078780
    Abstract: A semiconductor process includes the following steps. An interlayer is formed on a substrate. A first metallic oxide layer is formed on the interlayer. A reduction process is performed to reduce the first metallic oxide layer into a metal layer. A high temperature process is performed to transform the metal layer to a second metallic oxide layer.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Inventors: Chin-Fu Lin, Chih-Chien Liu, Teng-Chun Tsai, Chin-Cheng Chien, Chun-Yuan Wu
  • SEMICONDUCTOR PROCESS
    Publication number: 20130078778
    Abstract: A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • NON-PLANAR SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
    Publication number: 20130056827
    Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Inventors: Shih-Hung Tsai, Chien-Ting Lin, Chin-Cheng Chien, Chin-Fu Lin, Chih-Chien Liu, Teng-Chun Tsai, Chun-Yuan Wu
  • METAL GATE STRUCTURE AND FABRICATION METHOD THEREOF
    Publication number: 20130049141
    Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.
    Type: Application
    Filed: August 22, 2011
    Publication date: February 28, 2013
    Inventors: Tsun-Min Cheng, Min-Chuan Tsai, Chih-Chien Liu, Jen-Chieh Lin, Pei-Ying Li, Shao-Wei Wang, Mon-Sen Lin, Ching-Ling Lin
  • METHOD OF FORMING SEMICONDUCTOR DEVICE
    Publication number: 20130045579
    Abstract: A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 21, 2013
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME
    Publication number: 20130037886
    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.
    Type: Application
    Filed: August 10, 2011
    Publication date: February 14, 2013
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chih-Chien Liu, Chin-Cheng Chien, Chin-Fu Lin
  • Fin field-effect transistor structure and manufacturing process thereof
    Patent number: 8361854
    Abstract: A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: January 29, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien
  • SEMICONDUCTOR DEVICE
    Publication number: 20130020648
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a metal-oxide semiconductor (MOS) transistor disposed in the substrate; and a shallow trench isolation (STI) disposed in the substrate and around the MOS transistor, in which the STI comprises a stress material.
    Type: Application
    Filed: July 19, 2011
    Publication date: January 24, 2013
    Inventors: Chun-Yuan Wu, Chih-Chien Liu
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20130009288
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer comprises metal interconnects therein; forming a top metal layer on the dielectric layer; and forming a passivation layer on the top metal layer through high-density plasma chemical vapor deposition (HDPCVD) process.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 10, 2013
    Inventors: Shu-Hui Hu, Shih-Feng Su, Hui-Shen Shih, Chih-Chien Liu, Po-Chun Chen, Ya-Jyuan Hung, Bin-Siang Tsai, Chin-Fu Lin
  • FABRICATING METHOD OF MOS TRANSISTOR, FIN FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF
    Publication number: 20130001707
    Abstract: A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Inventors: Chien-Liang Lin, Ying-Wei Yen, Yu-Ren Wang, Chan-Lon Yang, Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
    Publication number: 20120319198
    Abstract: A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • THROUGH-SILICON VIA FORMING METHOD
    Publication number: 20120322260
    Abstract: A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien
  • Manufacturing method of metal gate structure
    Patent number: 8324118
    Abstract: A manufacturing method of a metal gate structure includes providing a substrate having at least a first metal oxide layer formed thereon, and transferring the surface of the first metal oxide layer into a second metal oxide layer. The first metal oxide layer includes a metal oxide (M1Ox) of a first metal (M1) and the second metal oxide layer includes a metal oxide ((M1M2Oy) of the first metal and a second metal (M2).
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: December 4, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Chun-Yuan Wu, Chin-Fu Lin, Teng-Chun Tsai, Chin-Cheng Chien
  • METHOD FOR FABRICATING HIGH-K DIELECTRIC LAYER
    Publication number: 20120282783
    Abstract: A method for fabricating high-k dielectric layer is disclosed. The method includes the steps of: providing a substrate; and forming a plurality of high-k dielectric layers by using a plurality of reacting gases to perform a plurality of process stages on the surface of the substrate, wherein at least one of the reacting gases comprises different flow rate in the fabrication stages.
    Type: Application
    Filed: May 3, 2011
    Publication date: November 8, 2012
    Inventors: Jui-Chen Chang, Chen-Kuo Chiang, Chin-Fu Lin, Chih-Chien Liu
  • COMPUTER BOOTING METHOD AND COMPUTER SYSTEM
    Publication number: 20120272095
    Abstract: A computer booting method is provided for a computer system. The method comprises performing a power-on-self test. When the test result shows no error on the BIOS, a booting procedure is executed. When the test result shows the BIOS is damaged, whether the computer system stores a backup file of the BIOS is determined. When the computer system stores the backup file, the central processing unit reads the data of backup file and write it into a BIOS system memory and a reboot process is performed. When there is no backup file in the computer system, the computer system is connected to an internet server and downloads a BIOS backup file to the system main memory from the internet server. The central processing unit reads the BIOS backup file and write it into the BIOS system memory and a reboot process is formed.
    Type: Application
    Filed: April 19, 2012
    Publication date: October 25, 2012
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chih-Chien Liu, Feng-Hsun Chen, Chia-Tsung Cheng
  • Method of Forming Opening on Semiconductor Substrate
    Publication number: 20120264306
    Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.
    Type: Application
    Filed: April 15, 2011
    Publication date: October 18, 2012
    Inventors: Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Po-Chun Chen
  • METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20120248507
    Abstract: A manufacturing method of a metal gate structure includes providing a substrate having at least a first metal oxide layer formed thereon, and transferring the surface of the first metal oxide layer into a second metal oxide layer. The first metal oxide layer includes a metal oxide (M1Ox) of a first metal (M1) and the second metal oxide layer includes a metal oxide ((M1M2Oy) of the first metal and a second metal (M2).
    Type: Application
    Filed: March 28, 2011
    Publication date: October 4, 2012
    Inventors: Chih-Chien Liu, Chun-Yuan Wu, Chin-Fu Lin, Teng-Chun Tsai, Chin-Cheng Chien