Abstract: A method of fabricating a shallow trench isolation structure is described. A preserve layer is formed on a substrate. A trench is formed in the substrate and the preserve layer. An oxide layer is formed over the substrate to fill the trench. A wet densification step is performed in a moist environment. A planarization step is performed until the preserve layer is exposed. A shallow trench isolation structure is formed.

Abstract: A method for forming dielectric layers is described. Wiring lines are formed on a provided semiconductor substrate. Spacers are formed on the sidewalls of the wiring lines. A liner layer is formed on the wiring lines and on the spacers by a first HDPCVD step, such as unbiased, unclamped HDPCVD. A dielectric layer is formed on the liner layer to cover the wiring lines and to fill gaps between the wiring lines by a second HDPCVD step.

Abstract: A method is used to form an intermetal dielectric layer. According to the invention, an unbiased-unclamped fluorinated silicate glass layer used as a protection layer is formed by high density plasma chemical vapor deposition on a biased-clamped fluorinated silicate glass layer formed by high density plasma chemical vapor deposition to prevent the biased-clamped fluorinated silicate glass layer from being exposed in a planarization process.

Abstract: A method for forming dielectric layers is described. Wiring lines are formed on a provided semiconductor substrate. Spacers are formed on the sidewalls of the wiring lines. A liner layer is formed on the wiring lines and on the spacers by a first HDPCVD step, such as unbiased, unclamped HDPCVD. A dielectric layer is formed on the liner layer to cover the wiring lines and to fill gaps between the wiring lines by a second HDPCVD step.

Abstract: A method for forming an inter-metal dielectric layer without voids therein is described. Wiring lines are formed on a provided substrate. Each of the wiring lines comprises a protective layer thereon. A liner layer is formed over the substrate and over the wiring lines. A fluorinated silicate glass (FSG) layer is formed on the liner layer by using high density plasma chemical vapor deposition (HDPCVD). A thickness of the FSG layer is about 0.9-1 times a thickness of the wiring lines. A cap layer is formed on the FSG layer using HDPCVD. A thickness of the cap layer is about 0.2-0.3 times a thickness of the wiring lines. An oxide layer is formed on the cap layer to achieve a predetermined thickness. A part of the dielectric layer is removed to obtain a planarized surface.

Abstract: A method for forming shallow trench isolation is disclosed. The method includes forming a trench in a semiconductor substrate, and then blanket depositing a silicon oxide layer over the semiconductor substrate by a plasma process, thereby substantially refilling the trench. Thereafter, a photoresist layer is formed on the plasma deposited silicon oxide layer, followed by etching back a portion of the photoresist layer. The plasma deposited silicon oxide layer is then isotropically etched, and the photoresist layer is then finally removed.

Abstract: A method of gap filling by using HDPCVD. On a substrate having a conductive structure, a first oxide layer is formed to protect the conductive structure. While forming the first oxide layer no bias is applied. An argon flow with a high speed of etching/deposition is provided to form a second oxide layer. While forming the second oxide layer a triangular or trapezium profile is formed due to an etching effect to the corner. An argon flow with a low speed of etching/deposition is provided to form a third oxide layer. The gap filling is completed.

Abstract: A method is used to form an intermetal dielectric layer. According to the invention, an unbiased-unclamped fluorinated silicate glass layer used as a protection layer is formed by high density plasma chemical vapor deposition on a biased-clamped fluorinated silicate glass layer formed by high density plasma chemical vapor deposition to prevent the biased-clamped fluorinated silicate glass layer from being exposed in a planarization process.

Abstract: A method for forming the copper interconnects is disclosed. The method includes, firstly, providing a semiconductor substrate is provided. Then, a first dielectric layer is formed. Sequentially, a second dielectric layer is formed and an anti-reflective layer is formed. Then, a hardmask layer is formed. Etching of the hardmask layer is carried out. The photoresist layer is removed and another photoresist is replaced. The anti-reflective layer, the second dielectric layer and the first dielectric layer are all etched. The hardmask layer, the anti-reflective layer and the second dielectric layer are all etched. The photoresist layer, the hardmask layer and the anti-reflective layer are all removed. A first barrier layer is conformably formed on the sidewalls and the exposed surfaces of the second dielectric layer and the first dielectric layer, and on the surface of the first copper layer. A seed layer is conformably formed on the barrier layer.

Abstract: A method for enhancing adhesion ability between copper and silicon nitride is disclosed. The present method comprises following steps: first, provide a substrate and then form a copper layer on the substrate; second, form a copper phosphide layer on the copper layer; and finally, form a silicon nitride layer on the copper phosphide layer. Herein, the copper phosphide layer is formed by a plasma enhanced chemical vapor deposition process. Therefore, any copper oxide layer that covers copper layer is replaced by the silicon phosphide layer and then adhesion between copper and silicon nitride is improved. Moreover, the silicon phosphide comprises two advantages: low resistance than copper oxide and efficiently prevent copper diffuses into surrounding dielectric layer.

Abstract: A method of fabricating shallow trench isolation (STI) forms a trench in a substrate and a liner oxide layer in the trench. A first high density plasma chemical vapor deposition (HDPCVD) is performed to form a conformal oxide layer on the liner oxide layer, without applying bias to the substrate. A second HDPCVD is then performed to form an oxide layer that fills the trench and covers the conformal oxide layer on the conformal oxide layer.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of dielectric layers using high density plasma chemical vapor deposition (HDPCVD). A first HDPCVD step is carried out to form a first dielectric layer over the wiring lines and into the gaps between wiring lines. A PECVD step is carried out to deposit dielectric material over the first dielectric layer and within and to define a opening in the gap. A second HDPCVD step is carried out and the opening defined by the PECVD step is capped by a third dielectric layer. The method allows air-filled voids to be formed between adjacent metal wiring lines in a highly controlled manner which allows selection of the shape of the voids and precise location of the top of the voids. In addition, the voids are sealed by a denser and more durable material than is typical.

Abstract: A method is described for manufacturing a multilevel metal interconnects. The method comprises the steps of providing a substrate and then forming a wire on the substrate. A dielectric layer is formed on the substrate and the wire and a protective layer is formed on the dielectric layer. An opening is formed by patterning the protective layer and the dielectric layer and a barrier layer is formed on the protective layer and in the opening. A copper layer is formed on the barrier layer and fills the opening. A portion of the copper layer and the barrier layer are removed by chemical-mechanical polishing.

Abstract: The present invention provides a method of forming an undoped silicate glass layer on a semiconductor wafer by performing a high density plasma chemical vapor deposition process. The semiconductor wafer being positioned in a deposition chamber. The method comprises forming the undoped silicate glass layer by performing the high density plasma chemical vapor deposition process in the deposition chamber under the following conditions: an argon (Ar) flow rate of 40 to 70 sccm (standard cubic centimeter per minute); an oxygen (O.sub.2) flow rate of 90 to 120 sccm; a silane flow rate of 70 to 100 sccm; a gas pressure of 3 to 10 mtorr; a temperature of 300 to 400.degree. C.; and a low frequency power of 2500 to 3500 watts. Wherein the ratio of Ar to O.sub.2 is 0.53, and O.sub.2 to silane is 1.23.

Abstract: A method of making vias in a semiconductor IC device having adequate contact to the surface of the interconnects and without inadequate landing is disclosed. The method has interconnects formed in a metal layer on the substrate of the IC device, and a first dielectric layer is formed covering the surface of the interconnects. An etch-stopping layer is then formed on top of the first dielectric layer, followed by the formation of a second dielectric layer on top of the etch-stopping layer. A photoresist layer then covers the second dielectric layer and reveals the surface regions of the second dielectric layer designated for the formation of the vias. A main etching procedure is then performed to etch into the second dielectric layer down to the surface of the etch-stopping layer, thereby forming the first section of the vias.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of three oxide layers using high density plasma chemical vapor deposition (HDPCVD). A first HDPCVD step is carried out while keeping the substrate unbiased to form an oxide layer over the lines and in the gap. A second HDPCVD step in which the substrate is biased deposits a second oxide layer over the first oxide layer. During the second HDPCVD step some etching occurs and a portion of the first oxide layer is removed. A third HDPCVD step is carried out at a greater etch and sputtering rate than the second step to complete filling of the gap with dielectric material. The first oxide layer acts to protect the underlying structures from etching damage during the third step. Gaps between wiring lines can be filled with dielectric material without forming voids, even for high aspect ratio gaps.