Abstract: The present application provides a semiconductor structure having vias with different dimensions and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; a second wafer including a second dielectric layer, a second substrate over the second dielectric layer, and a second conductive pad surrounded by the second dielectric layer; a passivation disposed over the second substrate; a first conductive via extending from the first conductive pad through the second wafer and the passivation, and having a first width surrounded by the second wafer; and a second conductive via extending from the second conductive pad through the passivation and the second substrate and partially through the second dielectric layer, and having a second width surrounded by the second wafer.

Abstract: A real time assay monitoring system and method can be used to monitor reagent volume in assays for fluid replenishment control, monitor assays in real-time to obtain quality control information, monitor assays in real-time during development to detect saturation levels that can be used to shorten assay time, and provide assay results before the assay is complete, enabling reflex testing to begin automatically. The monitoring system can include a real time imaging system with a camera and lights to capture images of the assay. The captured images can then be used to monitor and control the quality of the staining process in an assay, provide early assay results, and/or to measure the on-site reagent volume within the assay.

Abstract: A semiconductor device includes a substrate, a first film stack, a second film stack, a first gate spacer, a buffer layer, and a second gate spacer. The first and second film stacks are located on the substrate, and are respectively located in an array area and a periphery area. The first gate spacer includes a first portion on a sidewall of the first film stack and a second portion on a sidewall of the second film stack. The buffer layer includes a first portion on a sidewall of the first portion of the first gate spacer and a second portion on a sidewall of the second portion of the first gate spacer. The second gate spacer includes a first portion on a sidewall of the first portion of the buffer layer and a second portion on a sidewall the second portion of the buffer layer.

Abstract: The present application provides a memory device and a method of manufacturing the memory device. The method includes steps of providing a semiconductor substrate defined with an active area disposed over or in the semiconductor substrate; forming a first hard mask over the semiconductor substrate; forming a core over the first hard mask, wherein the core has a strip portion and a protruding portion protruding laterally from the strip portion; forming a spacer surrounding the core; removing the strip portion of the core; removing portions of the first hard mask exposed through the spacer and the protruding portion of the core; forming a second hard mask surrounding the first hard mask; removing the first hard mask; and removing portions of the semiconductor substrate exposed through the second hard mask to form a trench surrounding the active area.

Abstract: The present application provides a memory device and a method of manufacturing the memory device. The method includes steps of providing a semiconductor substrate defined with an active area disposed over or in the semiconductor substrate; forming a first hard mask over the semiconductor substrate; forming a core over the first hard mask, wherein the core has a strip portion and a protruding portion protruding laterally from the strip portion; forming a spacer surrounding the core; removing the strip portion of the core; removing portions of the first hard mask exposed through the spacer and the protruding portion of the core; forming a second hard mask surrounding the first hard mask; removing the first hard mask; and removing portions of the semiconductor substrate exposed through the second hard mask to form a trench surrounding the active area.

Abstract: The present application provides a memory device and a method of manufacturing the memory device. The method includes steps of providing a semiconductor substrate defined with an active area disposed over or in the semiconductor substrate; forming a first hard mask over the semiconductor substrate; forming a core over the first hard mask, wherein the core has a strip portion and a protruding portion protruding laterally from the strip portion; forming a spacer surrounding the core; removing the strip portion of the core; removing portions of the first hard mask exposed through the spacer and the protruding portion of the core; forming a second hard mask surrounding the first hard mask; removing the first hard mask; and removing portions of the semiconductor substrate exposed through the second hard mask to form a trench surrounding the active area.

Abstract: The present application provides a memory device and a method of manufacturing the memory device. The method includes steps of providing a semiconductor substrate defined with an active area disposed over or in the semiconductor substrate; forming a first hard mask over the semiconductor substrate; forming a core over the first hard mask, wherein the core has a strip portion and a protruding portion protruding laterally from the strip portion; forming a spacer surrounding the core; removing the strip portion of the core; removing portions of the first hard mask exposed through the spacer and the protruding portion of the core; forming a second hard mask surrounding the first hard mask; removing the first hard mask; and removing portions of the semiconductor substrate exposed through the second hard mask to form a trench surrounding the active area.

Abstract: A real time assay monitoring system and method can be used to monitor reagent volume in assays for fluid replenishment control, monitor assays in real-time to obtain quality control information, monitor assays in real-time during development to detect saturation levels that can be used to shorten assay time, and provide assay results before the assay is complete, enabling reflex testing to begin automatically. The monitoring system can include a real time imaging system with a camera and lights to capture images of the assay. The captured images can then be used to monitor and control the quality of the staining process in an assay, provide early assay results, and/or to measure the on-site reagent volume within the assay.

Abstract: The present application provides a method of manufacturing a semiconductor structure having vias with different dimensions and a manufacturing method of the semiconductor structure. The method includes: providing a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; providing a second wafer including a second dielectric layer, a second substrate over the second dielectric layer, and a second conductive pad surrounded by the second dielectric layer; forming a passivation over the second substrate; forming a first conductive via extending from the first conductive pad through the second wafer and the passivation, and having a first width surrounded by the second wafer; and forming a second conductive via extending from the second conductive pad through the passivation and the second substrate and partially through the second dielectric layer, and having a second width surrounded by the second wafer.

Abstract: The present application provides a semiconductor structure having vias with different dimensions and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; a second wafer including a second dielectric layer, a second substrate over the second dielectric layer, and a second conductive pad surrounded by the second dielectric layer; a passivation disposed over the second substrate; a first conductive via extending from the first conductive pad through the second wafer and the passivation, and having a first width surrounded by the second wafer; and a second conductive via extending from the second conductive pad through the passivation and the second substrate and partially through the second dielectric layer, and having a second width surrounded by the second wafer.

Abstract: A semiconductor structure includes a semiconductor device, an interconnect structure, a dielectric layer, and a redistribution layer (RDL). The interconnect structure is disposed over the semiconductor device. The dielectric layer is disposed over the interconnect structure. The RDL includes a conductive structure over the dielectric layer and a conductive via extending downwards from the conductive structure and through the dielectric layer. The conductive via includes a bottom portion, a top portion and a tapered portion between the bottom and top portions, in which the tapered portion has a width variation greater than that of the bottom and top portions.

Abstract: A real time assay monitoring system and method can be used to monitor reagent volume in assays for fluid replenishment control, monitor assays in real-time to obtain quality control information, monitor assays in real-time during development to detect saturation levels that can be used to shorten assay time, and provide assay results before the assay is complete, enabling reflex testing to begin automatically. The monitoring system can include a real time imaging system with a camera and lights to capture images of the assay. The captured images can then be used to monitor and control the quality of the staining process in an assay, provide early assay results, and/or to measure the on-site reagent volume within the assay.

Abstract: A real time assay monitoring system and method can be used to monitor reagent volume in assays for fluid replenishment control, monitor assays in real-time to obtain quality control information, monitor assays in real-time during development to detect saturation levels that can be used to shorten assay time, and provide assay results before the assay is complete, enabling reflex testing to begin automatically. The monitoring system can include a real time imaging system with a camera and lights to capture images of the assay. The captured images can then be used to monitor and control the quality of the staining process in an assay, provide early assay results, and/or to measure the on-site reagent volume within the assay.

Abstract: A real time assay monitoring system and method can be used to monitor reagent volume in assays for fluid replenishment control, monitor assays in real-time to obtain quality control information, monitor assays in real-time during development to detect saturation levels that can be used to shorten assay time, and provide assay results before the assay is complete, enabling reflex testing to begin automatically. The monitoring system can include a real time imaging system with a camera and lights to capture images of the assay. The captured images can then be used to monitor and control the quality of the staining process in an assay, provide early assay results, and/or to measure the on-site reagent volume within the assay.

Abstract: Disclosed is a guidance content automatic obtaining and displaying equipment, comprising an illustration data guidance content obtaining device, a illustration data displaying device and a guidance content displaying device in such a manner that, by utilizing a processor, the guidance content is automatically obtained from illustration data of a patent document and is displayed.

Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.

Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.

Abstract: A semiconductor structure includes a semiconductor device, an interconnect structure, a dielectric layer, and a redistribution layer (RDL). The interconnect structure is disposed over the semiconductor device. The dielectric layer is disposed over the interconnect structure. The RDL includes a conductive structure over the dielectric layer and a conductive via extending downwards from the conductive structure and through the dielectric layer. The conductive via includes a bottom portion, a top portion and a tapered portion between the bottom and top portions, in which the tapered portion has a width variation greater than that of the bottom and top portions.

Abstract: A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A patterned photoresist layer is formed over the dielectric layer, wherein the patterned photoresist layer has an opening exposing the dielectric layer. The dielectric layer is etched to form a via hole in the dielectric layer using the patterned photoresist layer as an etch mask. The opening of the patterned photoresist layer is laterally expanded. After the opening of the patterned photoresist layer is laterally expanded, the dielectric layer is etched to expand the via hole using the patterned photoresist layer as an etch mask. A conductive via is formed in the expanded via hole.

Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate, a plurality of metallic pillars, a plurality of metallic protrusions, a capping layer, and a passivation layer. The metallic pillars are disposed on the substrate. The metallic protrusions extend from an upper surface of the metallic pillars. The capping layer is disposed on the metallic protrusions. The passivation layer is disposed on sidewalls of the protrusions and the capping layer.