Patents by Inventor Chih-Ching Lin
Chih-Ching Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8748217Abstract: A method for manufacturing a thin film solar cell device includes forming a back contact layer on a substrate, forming an CIGS absorber layer on the back contact layer, treating the CIGS absorber layer with a metal-based alkaline solution, and forming a buffer layer on the CIGS absorber layer where the treatment of the CIGS absorber layer improves the adhesion between the CIGS absorber layer and the buffer layer and also improves the quality of the p-n junction at the CIGS absorber layer/buffer layer interface.Type: GrantFiled: November 13, 2012Date of Patent: June 10, 2014Assignee: TSMC Solar Ltd.Inventors: Chih-Ching Lin, Yong-Ping Chan, Kai-Yu Tung, Cheng-Tao Lee
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Publication number: 20140134784Abstract: A method for manufacturing a thin film solar cell device includes forming a back contact layer on a substrate, forming an CIGS absorber layer on the back contact layer, treating the CIGS absorber layer with a metal-based alkaline solution, and forming a buffer layer on the CIGS absorber layer where the treatment of the CIGS absorber layer improves the adhesion between the CIGS absorber layer and the buffer layer and also improves the quality of the p-n junction at the CIGS absorber layer/buffer layer interface.Type: ApplicationFiled: November 13, 2012Publication date: May 15, 2014Applicant: TSMC SOLAR LTD.Inventors: Chih-Ching LIN, Yong-Ping CHAN, Kai-Yu TUNG, Cheng-Tao LEE
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Publication number: 20140076392Abstract: A thin film solar cell and process for forming the same. The solar cell includes a bottom electrode layer, semiconductor light absorbing layer, and a TCO top electrode layer. In one embodiment, a TCO seed layer is formed between the top electrode and absorber layers to improve adhesion of the top electrode layer to the absorber layer. In one embodiment, the seed layer is formed at a lower temperature than the TCO top electrode layer and has a different microstructure.Type: ApplicationFiled: September 18, 2012Publication date: March 20, 2014Applicant: TSMC SOLAR LTD.Inventors: Chih Ching LIN, Yong-Ping CHAN, Wei-Chun HSU, Chen-Yun WANG
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Patent number: 8642479Abstract: A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.Type: GrantFiled: July 14, 2011Date of Patent: February 4, 2014Assignee: Nanya Technology CorporationInventors: Chih-Ching Lin, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8640074Abstract: A digital circuit block includes first to fourth conducting segments, a digital logic, first and second conducting layers, and a dielectric layer. The first and second conducting segments are coupled to first and second supply voltages, respectively. The digital logic and dielectric layer are between the first and second conducting segments. The third conducting segment includes a first end electrically connected to the first conducting segment, a second end not electrically connected to the second conducting segment, and a first portion located at the first conducting layer. The fourth conducting segment includes a first end electrically connected to the second conducting segment, a second end not electrically connected to the first conducting segment, and a second portion located at the second conducting layer. The first and second portions and dielectric layer are formed a first capacitive element to reduce the supply voltage drop between the first and second supply voltages.Type: GrantFiled: November 17, 2011Date of Patent: January 28, 2014Assignee: Mediatek Inc.Inventors: Shen-Yu Huang, Chih-Ching Lin
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Patent number: 8592320Abstract: A method for fabricating a fin-shaped semiconductor structure is provided, including: providing a semiconductor substrate with a semiconductor island and a dielectric layer formed thereover; forming a mask layer over the semiconductor island and the dielectric layer; forming an opening in the mask layer, exposing a top surface of the semiconductor island and portions of the dielectric layer adjacent to the semiconductor island; performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening; and removing the mask layer and the dielectric layer, leaving an etched semiconductor island with curved top surfaces and various thicknesses over the semiconductor substrate.Type: GrantFiled: August 15, 2011Date of Patent: November 26, 2013Assignee: Nanya Technology CorporationInventors: Chih-Ching Lin, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8389402Abstract: A method of via formation in a semiconductor device includes the following steps of providing a photoresist with a photoresist pattern defining an opening of a via, wherein the photoresist comprising a thermally cross-linking material is disposed on a structure layer; dry-etching the structure layer to a first depth through the opening; baking the thermally cross-linking material to reduce the opening; and dry-etching the structure layer to a second depth through the reduced opening, wherein the second depth is greater than the first depth.Type: GrantFiled: May 26, 2011Date of Patent: March 5, 2013Assignee: Nanya Technology CorporationInventors: Chih Ching Lin, Yi Nan Chen, Hsien Wen Liu
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Publication number: 20130045600Abstract: A method for fabricating a fin-shaped semiconductor structure is provided, including: providing a semiconductor substrate with a semiconductor island and a dielectric layer formed thereover; forming a mask layer over the semiconductor island and the dielectric layer; forming an opening in the mask layer, exposing a top surface of the semiconductor island and portions of the dielectric layer adjacent to the semiconductor island; performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening; and removing the mask layer and the dielectric layer, leaving an etched semiconductor island with curved top surfaces and various thicknesses over the semiconductor substrate.Type: ApplicationFiled: August 15, 2011Publication date: February 21, 2013Applicant: Nanya Technology CorporationInventors: Chih-Ching Lin, Yi-Nan Chen, Hsien-Wen Liu
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Publication number: 20130037934Abstract: An integrated circuit chip includes a power/ground interconnection network in a topmost metal layer over a semiconductor substrate and at least a bump pad on/over the power/ground interconnection network. The power/ground mesh interconnection network includes a first power/ground line connected to the bump pad and extending along a first direction, and a connection portion connected to the bump pad and extending along a second direction.Type: ApplicationFiled: August 9, 2011Publication date: February 14, 2013Inventors: Chih-Ching Lin, Ya-Ting Chang, Chia-Lin Chuang
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Publication number: 20130017687Abstract: A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.Type: ApplicationFiled: July 14, 2011Publication date: January 17, 2013Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Chih-Ching Lin, Yi-Nan Chen, Hsien-Wen Liu
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Publication number: 20120302065Abstract: The present invention relates to a pulse-plasma etching method and apparatus for preparing a depression structure with reduced bowing. The pulse-plasma etching apparatus comprises a container, an upper electrode plate, a lower electrode plate, a gas source, a first ultrahigh RF power supply, a bias RF power supply, and a pulsing module. When the pulsing module supplies an ultrahigh-frequency voltage between the upper electrode plate and the lower electrode plate, an ultrahigh-frequency voltage is switched to the off state, and a large amount of electrons pass through the plasma and reach the substrate to neutralize the positive ions during the duration of the off state (Toff).Type: ApplicationFiled: May 26, 2011Publication date: November 29, 2012Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Chih Ching Lin, Yi Nan Chen, Hsien Wen Liu
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Publication number: 20120302062Abstract: A method of via formation in a semiconductor device includes the following steps of providing a photoresist with a photoresist pattern defining an opening of a via, wherein the photoresist comprising a thermally cross-linking material is disposed on a structure layer; dry-etching the structure layer to a first depth through the opening; baking the thermally cross-linking material to reduce the opening; and dry-etching the structure layer to a second depth through the reduced opening, wherein the second depth is greater than the first depth.Type: ApplicationFiled: May 26, 2011Publication date: November 29, 2012Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Chih Ching Lin, Yi Nan Chen, Hsien Wen Liu
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Publication number: 20120302070Abstract: A method for performing pulse-etching in a semiconductor device includes the steps of providing a semiconductor substrate, wherein a metal layer is disposed on the semiconductor substrate, and a hard mask layer is blanketed over the metal layer; introducing the semiconductor substrate into a processing container; introducing, into the processing container, etching gases in which a deposition-type gas composed of at least two of C, H, and F is added to etching gas selected from the group consisting of Cl2 gas, BCl3 gas, HBr gas, and the combination thereof; applying a pulse-modulated high-frequency voltage between a pair of electrodes that are provided in the processing container so as to be opposed to each other and to hold the semiconductor substrate, such that the high-frequency voltage is turned on and off to establish a duty ratio; generating a plasma between the pair of electrodes; and etching the semiconductor substrate using the plasma.Type: ApplicationFiled: May 26, 2011Publication date: November 29, 2012Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Chih Ching Lin, Yi Nan Chen, Hsien Wen Liu
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Publication number: 20120283802Abstract: The present invention provides a novel use of far-infrared radiation for improving patency of arteriovenous fistula, decreasing failure of arteriovenous fistula maturation and preventing and/or ameliorating peripheral artery diseases in a subject in need thereof. The radiation has an electromagnetic wave of about 1.5 to 100 ?m wavelength, which performs on the subject skin surface for more than 10 minutes.Type: ApplicationFiled: July 20, 2012Publication date: November 8, 2012Inventors: Chih-Ching LIN, Chyi-Ran LEE
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Publication number: 20120056488Abstract: A digital circuit block includes first to fourth conducting segments, a digital logic, first and second conducting layers, and a dielectric layer. The first and second conducting segments are coupled to first and second supply voltages, respectively. The digital logic and dielectric layer are between the first and second conducting segments. The third conducting segment includes a first end electrically connected to the first conducting segment, a second end not electrically connected to the second conducting segment, and a first portion located at the first conducting layer. The fourth conducting segment includes a first end electrically connected to the second conducting segment, a second end not electrically connected to the first conducting segment, and a second portion located at the second conducting layer. The first and second portions and dielectric layer are formed a first capacitive element to reduce the supply voltage drop between the first and second supply voltages.Type: ApplicationFiled: November 17, 2011Publication date: March 8, 2012Inventors: Shen-Yu Huang, Chih-Ching Lin
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Patent number: 7949988Abstract: A layout circuit is provided, comprising standard cells, a spare cell, combined tie cells and normal filler cells. The standard cells are disposed and routed on a layout area. The spare cell is added on the layout area and provided for replacing one of the standard cells while adding or changing functions later. The combined tie cells are added on the layout area. The normal filler cells are added on the rest of the layout area. The combined tie cell comprises a tie-high circuit, a tie-low circuit and a capacitance circuit. Some standard cells are disposed near at least one combined tie cell for avoiding routing congestion between the combined tie cells and the replaced standard cell. A circuit layout method is also provided.Type: GrantFiled: April 1, 2008Date of Patent: May 24, 2011Assignee: Mediatek Inc.Inventors: Tung-Kai Tsai, Chih-Ching Lin
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Publication number: 20100181847Abstract: A method for reducing a supply voltage drop in a digital circuit block, where the digital circuit block includes a first conducting segment coupled to a first supply voltage, a second conducting segment coupled to a second supply voltage, and a digital logic coupled between the first conducting segment and the second conducting segment, the method including: constructing a third conducting segment connected to the first conducting segment and not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a first conducting layer; and constructing a fourth conducting segment electrically connected to the second conducting segment and not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at a second conducting layer, and whereby a capacitive element is formed between the first portion and the second portion.Type: ApplicationFiled: January 22, 2009Publication date: July 22, 2010Inventors: Shen-Yu Huang, Chih-Ching Lin
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Patent number: 7678692Abstract: A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.Type: GrantFiled: November 28, 2006Date of Patent: March 16, 2010Assignee: Nanya Technology CorporationInventors: Yi-Nan Chen, Jeng-Ping Lin, Chih-Ching Lin, Hui-Min Mao
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Publication number: 20090249273Abstract: A layout circuit is provided, comprising standard cells, a spare cell, combined tie cells and normal filler cells. The standard cells are disposed and routed on a layout area. The spare cell is added on the layout area and provided for replacing one of the standard cells while adding or changing functions later. The combined tie cells are added on the layout area. The normal filler cells are added on the rest of the layout area. The combined tie cell comprises a tie-high circuit, a tie-low circuit and a capacitance circuit. Some standard cells are disposed near at least one combined tie cell for avoiding routing congestion between the combined tie cells and the replaced standard cell. A circuit layout method is also provided.Type: ApplicationFiled: April 1, 2008Publication date: October 1, 2009Applicant: MEDIATEK INC.Inventors: Tung-Kai Tsai, Chih-Ching Lin
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Publication number: 20090124079Abstract: A method for fabricating a conductive plug includes the steps of providing a substrate having at least a gate structure thereon, a first dielectric layer covering a surface of the substrate, a second dielectric layer disposed on the first dielectric layer, and at least a metal line formed within the second dielectric layer; forming a hard mask plug on the second dielectric layer; forming a third dielectric layer covering the second dielectric layer and the hard mask plug; removing a portion of the third dielectric layer to expose the hard mask plug; removing the hard mask plug to form a plug hole; and forming the conductive plug within the plug hole to electrically connect with the gate structure.Type: ApplicationFiled: March 5, 2008Publication date: May 14, 2009Inventors: Jen-Jui Huang, Chih-Ching Lin, Kuo-Chung Chen