Abstract: Methods, systems, and apparatus for wirelessly providing power to a vehicle. The system includes a plurality of ground-side wireless power transfer devices each configured to automatically provide power to a counterpart vehicle-side wireless power transfer device. The system includes a switch connecting a power source to the plurality of ground-side wireless power transfer devices and configured to be in an open position or a closed position. The system includes a vehicle position sensor configured to detect the vehicle being within a range of the plurality of ground-side wireless power transfer devices. The system includes a switch driver configured to move the switch from the open position to the closed position when the vehicle position sensor detects the vehicle being within the range, and move the switch from the closed position to the open position when the vehicle position sensor does not detect the vehicle being within the range.

Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

Abstract: A backlight module includes a light guide panel and a backlight source, which emits light entering the light guide panel via a light receiving surface on a side of the light guide panel. The backlight source includes a base plate and a plurality of light source holders disposed on the base plate. The light source holder includes a circuit substrate having an opening and a base surface. The base surface and the opening are transitionally connected by a curved surface.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.

Abstract: A method of preparing a thermoplastic composition is provided. The method includes the following steps. A polyetherimide or a polyphenylene sulfide is provided. A polyimide is provided, wherein the glass transition temperature of the polyimide is between 128° C. and 169° C., the 10% thermogravimetric loss temperature of the polyimide is between 490° C. and 534° C., and when the polyimide is dissolved in N-methyl-2-pyrrolidone and the solid content of the polyimide is 30 wt %, the viscosity of the polyimide is between 100 cP and 250 cP. A melt process is performed to mix the polyetherimide and the polyimide or mix the polyphenylene sulfide and the polyimide to form a thermoplastic composition. Further, a thermoplastic composition is also provided.

Abstract: A display assembling mechanism is applied to a display apparatus. The display assembling mechanism includes a bracket, a front frame and a rear frame. The bracket is configured to accommodate an optical film assembly. The front frame has a main body and a pressing portion connected with each other. A touch module is disposed inside the main body, and the pressing portion is configured to fix an optical component assembly above the bracket. The rear frame is disposed on a side of the bracket opposite to the optical component assembly, and is locked on the front frame to cover the bracket.

Abstract: A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.

Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage region and a high voltage region are integrated in a substrate. A low voltage transistor device is disposed in the low voltage region and comprises a low voltage gate electrode and a low voltage gate dielectric separating the low voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage gate electrode and the low voltage gate dielectric. A high voltage transistor device is disposed in the high voltage region and comprises a high voltage gate electrode disposed on the first interlayer dielectric layer.

Abstract: A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.

Abstract: Some embodiments relate to an integrated circuit (IC) that includes a semiconductor substrate. A shallow trench isolation region downwardly extends into the frontside of the semiconductor substrate and is filled with dielectric material. A first capacitor plate and a second capacitor plate are disposed in the shallow trench isolation region. The first capacitor plate and the second capacitor plate have first and second sidewall structures, respectively, that are substantially parallel to one another and that are separated from one another by the dielectric material of the shallow trench isolation region.

Abstract: A preparation method of separation membrane is provided. First, a polyimide composition including a dissolvable polyimide, a crosslinking agent, and a solvent is provided. The dissolvable polyimide is represented by formula 1: wherein B is a tetravalent organic group derived from a tetracarboxylic dianhydride containing aromatic group, A is a divalent organic group derived from a diamine containing aromatic group, A? is a divalent organic group derived from a diamine containing aromatic group and carboxylic acid group, and 0.1?X?0.9. The crosslinking agent is an aziridine crosslinking agent, an isocyanate crosslinking agent, an epoxy crosslinking agent, a diamine crosslinking agent, or a triamine crosslinking agent. A crosslinking process is performed on the polyimide composition. The polyimide composition which has been subjected to the crosslinking process is coated on a substrate to form a polyimide membrane. A dry phase inversion process is performed on the polyimide membrane.

Abstract: A method is provided. A library associated with a cell is received. A minimum setup time of the cell is acquired in response to an ideal hold time according to the library and a reference clock. A maximum hold time of the cell is acquired in response to the minimum setup time according to the library and the reference clock. A plurality of candidate hold times are determined. A plurality of candidate setup times are acquired corresponding to the plurality of candidate hold times according to the library and the reference clock. The plurality of candidate setup times are added to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows. A target time window is selected that has a minimal time span among the candidate time windows.

Abstract: In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

Abstract: In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

Abstract: A preparation method of separation membrane is provided. First, a polyimide composition including a dissolvable polyimide, a crosslinking agent, and a solvent is provided. The dissolvable polyimide is represented by formula 1: wherein B is a tetravalent organic group derived from a tetracarboxylic dianhydride containing aromatic group, A is a divalent organic group derived from a diamine containing aromatic group, A? is a divalent organic group derived from a diamine containing aromatic group and carboxylic acid group, and 0.1?X?0.9. The crosslinking agent is an aziridine crosslinking agent, an isocyanate crosslinking agent, an epoxy crosslinking agent, a diamine crosslinking agent, or a triamine crosslinking agent. A crosslinking process is performed on the polyimide composition. The polyimide composition which has been subjected to the crosslinking process is coated on a substrate to form a polyimide membrane. A dry phase inversion process is performed on the polyimide membrane.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.

Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage transistor device is disposed in a low voltage region defined on a substrate. The low voltage transistor device comprises a low voltage gate electrode and a first gate dielectric separating the low voltage gate electrode from the substrate. A high voltage transistor device is disposed in a high voltage region defined on the substrate. The high voltage transistor device comprises a high voltage gate electrode and a high voltage gate dielectric separating the high voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage transistor device and the high voltage transistor device. The high voltage gate electrode is disposed on the first interlayer dielectric layer and separated from the substrate by the first interlayer dielectric layer.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.

Abstract: An integrated circuit having an epitaxial source and drain, which reduces gate burnout and increases switching speed so that is suitable for high voltage applications, is provided. The integrated circuit includes a semiconductor substrate having a high voltage N-well (HVNW) and a high voltage P-well (HVPW). The integrated circuit further includes a high-voltage device on the semiconductor substrate. The high-voltage device includes an epitaxial p-type source disposed in the HVNW, an epitaxial p-type drain disposed in the HVPW, and a gate arranged between the epitaxial p-type source and the epitaxial p-type drain on a surface of the semiconductor substrate.