Patents by Inventor Chih Chou

Chih Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11404613
    Abstract: A light emitting diode package structure and a manufacturing method thereof and a display device are provided. The light emitting diode package structure includes a blue light emitting diode and a phosphor layer. The phosphor layer is disposed on the blue light emitting diode package structure, and the phosphor layer includes an encapsulation layer and a plurality of phosphor powders. The phosphor powders are disposed in the encapsulation layer and consist of green phosphor powders, red phosphor powders, and yellow phosphor powders, in which a weight percentage of the yellow phosphor powders ranges from 1% to 10%.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 2, 2022
    Assignee: Wistron Corporation
    Inventors: Zhiyi Liang, Chih-Chou Chou, Wei-Chia Huang
  • Publication number: 20220178071
    Abstract: A non-woven film for electronic components is provided in the present disclosure. The non-woven film for electronic components includes a polyetherimide substrate and an aerogel. The aerogel is disposed on the polyetherimide substrate. The aerogel has a moisture content between 0.7% and 0.9% and a porosity between 85% and 95%.
    Type: Application
    Filed: December 2, 2021
    Publication date: June 9, 2022
    Inventors: Shao-Yen CHANG, Shang-Chih CHOU, Chun-Hung LIN
  • Publication number: 20220160127
    Abstract: A slide rail assembly includes a first rail, a second rail, and a third rail. The first rail includes a supporting feature. The second rail can be displaced with respect to the first rail. The third rail is movably disposed between the first rail and the second rail. When the slide rail assembly is in a predetermined state, the supporting feature protrudes beyond an end portion of the third rail by a predetermined distance and supports the second rail.
    Type: Application
    Filed: February 19, 2021
    Publication date: May 26, 2022
    Inventors: KEN-CHING CHEN, SHUN-HO YANG, CHI-CHIH CHOU, CHUN-CHIANG WANG
  • Patent number: 11315503
    Abstract: A liquid crystal display panel is provided. The liquid crystal display panel includes a liquid crystal display panel, a backlight module and a control circuit. The control circuit is coupled to the liquid crystal display panel and the backlight module. The control circuit is configured to control the liquid crystal display panel to display a corresponding image according to image data, and control the backlight module to provide backlight to the liquid crystal display panel. The control circuit determines a turn-on time point of each of a plurality of zones of the backlight module according to a response time of the liquid crystal display panel and a writing period of at least one target display area of the liquid crystal display panel. The control circuit further determines the turn-on time length of each zone according to the image data corresponding to the grayscale data of each zone.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: April 26, 2022
    Assignee: Wistron Corporation
    Inventors: Yuanliang Liu, Junxin Qiu, Lixing Zhu, Mingyue Geng, Chih-Chou Chou
  • Patent number: 11302691
    Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage region and a high voltage region are integrated in a substrate. A low voltage transistor device is disposed in the low voltage region and comprises a low voltage gate electrode and a low voltage gate dielectric separating the low voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage gate electrode and the low voltage gate dielectric. A high voltage transistor device is disposed in the high voltage region and comprises a high voltage gate electrode disposed on the first interlayer dielectric layer.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kong-Beng Thei, Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky, Yi-Sheng Chen
  • Publication number: 20220102518
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 31, 2022
    Inventors: Yi-Huan Chen, Kong-Beng Thei, Chien-Chih Chou, Alexander Kalnitsky, Szu-Hsien Liu, Huan-Chih Yuan
  • Publication number: 20220084174
    Abstract: A target image of a target circuit board and a gold image of a gold circuit board are taken by an image acquisition system. Fiducial points are located on the target image and on the gold image. Perspective transformation is performed on the target image using the fiducial points on the target image for reference and on the gold image using the fiducial points on the gold image for reference. After perspective transformation, an anomalous section of the target image is identified by identifying pixels that have different intensities between the target image and the gold image, the anomalous section being indicative of an unauthorized modification to the target circuit board.
    Type: Application
    Filed: September 11, 2020
    Publication date: March 17, 2022
    Applicant: Super Micro Computer, Inc.
    Inventors: Bo-Han WO, Chun-Yi LIN, Yu-Lung SHIH, Kai Cheng WEN, Kevin Wei-Chou CHEN, Yu-Jung LIANG, Pei Hsiang YANG, Jenn-Chih CHOU
  • Patent number: 11276684
    Abstract: Some embodiments relate to an integrated circuit (IC) that includes a semiconductor substrate. A shallow trench isolation region downwardly extends into the frontside of the semiconductor substrate and is filled with dielectric material. A first capacitor plate and a second capacitor plate are disposed in the shallow trench isolation region. The first capacitor plate and the second capacitor plate have first and second sidewall structures, respectively, that are substantially parallel to one another and that are separated from one another by the dielectric material of the shallow trench isolation region.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Kong-Beng Thei
  • Patent number: 11270052
    Abstract: A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia Hao Tu, Hsueh-Chih Chou, Sang Hoo Dhong, Jerry Chang Jui Kao, Chi-Lin Liu, Cheng-Chung Lin, Shang-Chih Hsieh
  • Patent number: 11266237
    Abstract: A slide rail assembly includes a first rail, a second rail, a contact structure and a locking device. The second rail is movable relative to the first rail. The contact structure is arranged on the second rail. The locking device is arranged on the first rail and includes a working member configured to be in a blocking state or an unblocking state relative to the first rail. When the second rail is located at a retracted position and when the working member is in the blocking state, the working member is configured to block the contact structure, in order to prevent the second rail from being moved relative to the first rail from the retracted position along an opening direction.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: March 8, 2022
    Assignees: King Slide Works Co., Ltd., King Slide Technology Co., Ltd.
    Inventors: Ken-Ching Chen, Shun-Ho Yang, Chi-Chih Chou, Chun-Chiang Wang
  • Publication number: 20220065292
    Abstract: A slide rail assembly includes a first rail, a second rail, a blocking feature, and a component. The two rails can be displaced with respect to each other. The blocking feature is provided at one of the two rails, and the component at the other of the two rails. When the second rail is at a predetermined position with respect to the first rail, a blocking portion of the blocking feature and a predetermined portion of the component are blocked by each other to prevent the second rail from being displaced with respect to the first rail from the predetermined position in a predetermined direction. One of the blocking portion and the predetermined portion forms a non-vertical structure.
    Type: Application
    Filed: December 3, 2020
    Publication date: March 3, 2022
    Inventors: KEN-CHING CHEN, SHUN-HO YANG, CHI-CHIH CHOU, CHUN-CHIANG WANG
  • Patent number: 11251286
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kong-Beng Thei, Chien-Chih Chou, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky
  • Patent number: 11246410
    Abstract: A slide rail assembly includes a first rail, a second rail, a stop, and a working member. The second rail can be displaced with respect to the first rail. The stop is disposed on the first rail. The working member is movably mounted on the second rail. When reaching a predetermined position after being displaced with respect to the first rail from an extended position in a retracting direction, the second rail is blocked by the stop via the working member and is thus prevented from being displaced from the predetermined position in an opening direction. The slide rail assembly has a shorter length when the second rail is at the predetermined position than when the second rail is at the extended position.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: February 15, 2022
    Assignees: King Slide Works Co., Ltd., King Slide Technology Co., Ltd.
    Inventors: Ken-Ching Chen, Shun-Ho Yang, Chi-Chih Chou, Chun-Chiang Wang
  • Patent number: 11235287
    Abstract: A preparation method of separation membrane is provided. First, a polyimide composition including a dissolvable polyimide, a crosslinking agent, and a solvent is provided. The dissolvable polyimide is represented by formula 1: wherein B is a tetravalent organic group derived from a tetracarboxylic dianhydride containing aromatic group, A is a divalent organic group derived from a diamine containing aromatic group, A? is a divalent organic group derived from a diamine containing aromatic group and carboxylic acid group, and 0.1?X?0.9. The crosslinking agent is an aziridine crosslinking agent, an isocyanate crosslinking agent, an epoxy crosslinking agent, a diamine crosslinking agent, or a triamine crosslinking agent. A crosslinking process is performed on the polyimide composition. The polyimide composition which has been subjected to the crosslinking process is coated on a substrate to form a polyimide membrane. A dry phase inversion process is performed on the polyimide membrane.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Textile Research Institute
    Inventors: Shang-Chih Chou, Chun-Hung Chen, Chun-Hung Lin, Kueir-Rarn Lee
  • Patent number: 11229885
    Abstract: A preparation method of separation membrane is provided. First, a polyimide composition including a dissolvable polyimide, a crosslinking agent and a solvent is provided. The dissolvable polyimide is represented by formula 1: wherein B is a tetravalent organic group derived from a tetracarboxylic dianhydride containing aromatic group, A is a divalent organic group derived from a diamine containing aromatic group, A? is a divalent organic group derived from a diamine containing aromatic group and carboxylic acid group, and 0.1?X?0.9. The crosslinking agent is an aziridine crosslinking agent, an isocyanate crosslinking agent, an epoxy crosslinking agent, a diamine crosslinking agent, or a triamine crosslinking agent. A crosslinking process is performed on the polyimide composition. The polyimide composition which has been subjected to the crosslinking process is coated on a substrate to form a polyimide membrane. A wet phase inversion process is performed on the polyimide membrane.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: January 25, 2022
    Assignee: Taiwan Textile Research Institute
    Inventors: Shang-Chih Chou, Chun-Hung Chen, Chun-Hung Lin, Kueir-Rarn Lee
  • Publication number: 20220005983
    Abstract: A light emitting diode package structure and a manufacturing method thereof and a display device are provided. The light emitting diode package structure includes a blue light emitting diode and a phosphor layer. The phosphor layer is disposed on the blue light emitting diode package structure, and the phosphor layer includes an encapsulation layer and a plurality of phosphor powders. The phosphor powders are disposed in the encapsulation layer and consist of green phosphor powders, red phosphor powders, and yellow phosphor powders, in which a weight percentage of the yellow phosphor powders ranges from 1% to 10%.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 6, 2022
    Inventors: Zhiyi Liang, Chih-Chou Chou, Wei-Chia Huang
  • Publication number: 20210384082
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure over a substrate. A metal layer overlies the gate dielectric structure. A conductive layer overlies the metal layer. A polysilicon layer contacts opposing sides of the conductive layer. A bottom surface of the polysilicon layer is aligned with a bottom surface of the conductive layer. A dielectric layer overlies the polysilicon layer. The dielectric layer continuously extends from sidewalls of the polysilicon layer to an upper surface of the conductive layer.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 9, 2021
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Chia-Hong Wu
  • Patent number: 11183128
    Abstract: A liquid crystal display and a display calibration method thereof are provided. The display calibration method includes the following steps. A liquid crystal display panel is driven by a driving circuit to display an image. A light-emitting diode backlight module is driven by the driving circuit to provide a backlight to the liquid crystal display panel, wherein the driving circuit determines at least one illuminating time of the light-emitting diode backlight module according to a response time of the liquid crystal display panel and a writing period of at least one target display area of the liquid crystal display panel.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: November 23, 2021
    Assignee: Wistron Corporation
    Inventors: Yueqi Xu, Chih-Chou Chou, Junxin Qiu, Yongqiang Li, Wenzhi Wang
  • Publication number: 20210301426
    Abstract: A fiber masterbatch including a polyetherimide, a polyethylene terephthalate, and a polyimide is provided. A glass transition temperature of the polyimide is between 140° C. and 170° C., a 10% thermogravimetric loss temperature of the polyimide is between 500° C. and 550° C., and when the polyimide is dissolved in N-methyl-2-pyrrolidone and a solid content of the polyimide is 15 wt %, a viscosity of the polyimide is between 80 cP and 230 cP. A melt spun fiber obtained by using the fiber masterbatch is also provided.
    Type: Application
    Filed: September 29, 2020
    Publication date: September 30, 2021
    Applicant: Taiwan Textile Research Institute
    Inventors: Shang-Chih Chou, Shao-Yen Chang, Chun-Hung Lin, Yuan-Pei Liao, Yi-Cang Lai
  • Publication number: 20210298473
    Abstract: A slide rail assembly includes a first rail, a second rail, a contact structure and a locking device. The second rail is movable relative to the first rail. The contact structure is arranged on the second rail. The locking device is arranged on the first rail and includes a working member configured to be in a blocking state or an unblocking state relative to the first rail. When the second rail is located at a retracted position and when the working member is in the blocking state, the working member is configured to block the contact structure, in order to prevent the second rail from being moved relative to the first rail from the retracted position along an opening direction.
    Type: Application
    Filed: July 23, 2020
    Publication date: September 30, 2021
    Inventors: Ken-Ching Chen, Shun-Ho Yang, Chi-Chih Chou, Chun-Chiang Wang