Patents by Inventor Chih Chou

Chih Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200238220
    Abstract: A preparation method of separation membrane is provided. First, a polyimide composition including a dissolvable polyimide, a crosslinking agent and a solvent is provided. The dissolvable polyimide is represented by formula 1: wherein B is a tetravalent organic group derived from a tetracarboxylic dianhydride containing aromatic group, A is a divalent organic group derived from a diamine containing aromatic group, A? is a divalent organic group derived from a diamine containing aromatic group and carboxylic acid group, and 0.1?X?0.9. The crosslinking agent is an aziridine crosslinking agent, an isocyanate crosslinking agent, an epoxy crosslinking agent, a diamine crosslinking agent, or a triamine crosslinking agent. A crosslinking process is performed on the polyimide composition. The polyimide composition which has been subjected to the crosslinking process is coated on a substrate to form a polyimide membrane. A wet phase inversion process is performed on the polyimide membrane.
    Type: Application
    Filed: April 16, 2020
    Publication date: July 30, 2020
    Applicant: Taiwan Textile Research Institute
    Inventors: Shang-Chih Chou, Chun-Hung Chen, Chun-Hung Lin, Kueir-Rarn Lee
  • Patent number: 10685982
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsueh-Chih Chou, Chia Hao Tu, Sang Hoo Dhong, Lee-Chung Lu, Li-Chun Tien, Ting-Wei Chiang, Hui-Zhong Zhuang
  • Patent number: 10675590
    Abstract: A preparation method of separation membrane is provided. First, a polyimide composition including a dissolvable polyimide, a crosslinking agent and a solvent is provided. The dissolvable polyimide is represented by formula 1: wherein B is a tetravalent organic group derived from a tetracarboxylic dianhydride containing aromatic group, A is a divalent organic group derived from a diamine containing aromatic group, A? is a divalent organic group derived from a diamine containing aromatic group and carboxylic acid group, and 0.1?X?0.9. The crosslinking agent is an aziridine crosslinking agent, an isocyanate crosslinking agent, an epoxy crosslinking agent, a diamine crosslinking agent, or a triamine crosslinking agent. A crosslinking process is performed on the polyimide composition. The polyimide composition which has been subjected to the crosslinking process is coated on a substrate to form a polyimide membrane. A wet phase inversion process is performed on the polyimide membrane.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 9, 2020
    Assignee: Taiwan Textile Research Institute
    Inventors: Shang-Chih Chou, Chun-Hung Chen, Chun-Hung Lin, Kueir-Rarn Lee
  • Publication number: 20200144263
    Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region, and a method of formation. In some embodiments, the integrated circuit comprises a first gate boundary dielectric layer disposed over a substrate in the low voltage region. A second gate boundary dielectric layer is disposed over the substrate in the high voltage region having a thickness greater than that of the first boundary dielectric layer. The first boundary dielectric layer meets the second boundary dielectric layer at the boundary region. A first polysilicon component is disposed within the boundary region over the first boundary dielectric layer and the second gate boundary layer. A second polysilicon component is disposed within the boundary region over the first polysilicon component. A hard mask component is disposed over the first polysilicon component and laterally neighbored to the second polysilicon component.
    Type: Application
    Filed: January 2, 2020
    Publication date: May 7, 2020
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Kong-Beng Thei
  • Publication number: 20200126870
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a fully silicided (FUSI) gated device, the method including: forming a masking layer onto a gate structure over a substrate, the gate structure comprising a polysilicon layer. Forming a first source region and a first drain region on opposing sides of the gate structure within the substrate, the gate structure is formed before the first source and drain regions. Performing a first removal process to remove a portion of the masking layer and expose an upper surface of the polysilicon layer. The first source and drain regions are formed before the first removal process. Forming a conductive layer directly contacting the upper surface of the polysilicon layer. The conductive layer is formed after the first removal process. Converting the conductive layer and polysilicon layer into a FUSI layer. The FUSI layer is thin and uniform in thickness.
    Type: Application
    Filed: October 24, 2018
    Publication date: April 23, 2020
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Chia-Hong Wu
  • Patent number: 10625216
    Abstract: A polyimide mixture including a polyimide and an amino-containing silica particle is provided. The polyimide includes a repeating unit represented by formula 1: wherein Ar includes and A includes The amino-containing silica particle is mixed with the polyimide, and is obtained by the hydrolysis condensation reaction of an alkoxysilane shown in formula 2 and an alkoxysilane shown in formula 3 in the presence of a catalyst: Si(OR1)4??formula 2, (NH2—Y)m—Si(OR2)4-m??formula 3, wherein in formula 2, R1 is a C1-C10 alkyl group; and in formula 3, Y is a C1-C10 alkyl group or a C2-C10 alkenyl group, R2 is a C1-C10 alkyl group, and m is an integer of 1 to 3.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: April 21, 2020
    Assignee: Taiwan Textile Research Institute
    Inventors: Shang-Chih Chou, Chun-Hung Chen, Chien-Chieh Hu
  • Patent number: 10627855
    Abstract: A display device includes a backlight module, a rear casing, an outer bezel frame, and a panel module. The backlight module includes a back plate and a light emitting assembly disposed on the back plate for emitting light. The rear casing covers the backlight module. The outer bezel frame includes a bezel body, a first fixing portion and a second fixing portion. The first fixing portion and the second fixing portion are disposed on a rear side of the bezel body and spaced apart from each other in a lateral direction. The second fixing portion is located at a side of the first fixing portion away from the backlight module. The first fixing portion and the second fixing portion are respectively fixed to the back plate and the rear casing in the lateral direction. The panel module is fixed on a front side of the bezel body for displaying images.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: April 21, 2020
    Assignee: Wistron Corporation
    Inventors: Guo-Wei Huang, Wei-Chia Huang, Chih-Chou Chou, Yao-Chen Yang
  • Publication number: 20200110912
    Abstract: A method is provided. A library associated with a cell is received. A minimum setup time of the cell is acquired in response to an ideal hold time according to the library and a reference clock. A maximum hold time of the cell is acquired in response to the minimum setup time according to the library and the reference clock. A plurality of candidate hold times are determined. A plurality of candidate setup times are acquired corresponding to the plurality of candidate hold times according to the library and the reference clock. The plurality of candidate setup times are added to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows. A target time window is selected that has a minimal time span among the candidate time windows.
    Type: Application
    Filed: September 23, 2019
    Publication date: April 9, 2020
    Inventors: CHIA HAO TU, HSUEH-CHIH CHOU, SANG HOO DHONG, JERRY CHANG JUI KAO, CHI-LIN LIU, CHENG-CHUNG LIN, SHANG-CHIH HSIEH
  • Publication number: 20200101711
    Abstract: The present invention provides a method of laminating a film for a dye-sensitized cell. First, a composite film is taken by a robotic arm, in which the composite film includes a release layer, a protective layer and a hot glue layer between the release layer and the protective layer, and the release layer is removed by the robotic arm. Then, the hot glue layer is precisely attached to a substrate by a target positioning step. Next, the protective layer is removed by the robotic arm.
    Type: Application
    Filed: October 2, 2019
    Publication date: April 2, 2020
    Inventors: Ching-Fu CHEN, Hao-Wei CHEN, Kun-Tai HO, Wan-Tun HUNG, Po-Min CHEN, Liang-Kun HUANG, Chih-Chou CHANG, Yung-Liang TUNG, Po-Tsung HSIAO, Ming-De LU
  • Publication number: 20200105748
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.
    Type: Application
    Filed: May 15, 2019
    Publication date: April 2, 2020
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo
  • Publication number: 20200091310
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 19, 2020
    Inventors: Kong-Beng Thei, Chien-Chih Chou, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky
  • Publication number: 20200081482
    Abstract: A display device includes a backlight module, a rear casing, an outer bezel frame, and a panel module. The backlight module includes a back plate and a light emitting assembly disposed on the back plate for emitting light. The rear casing covers the backlight module. The outer bezel frame includes a bezel body, a first fixing portion and a second fixing portion. The first fixing portion and the second fixing portion are disposed on a rear side of the bezel body and spaced apart from each other in a lateral direction. The second fixing portion is located at a side of the first fixing portion away from the backlight module. The first fixing portion and the second fixing portion are respectively fixed to the back plate and the rear casing in the lateral direction. The panel module is fixed on a front side of the bezel body for displaying images.
    Type: Application
    Filed: December 19, 2018
    Publication date: March 12, 2020
    Inventors: Guo-Wei Huang, Wei-Chia Huang, Chih-Chou Chou, Yao-Chen Yang
  • Publication number: 20200083343
    Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
  • Publication number: 20200055988
    Abstract: A poly(amide-imide) is provided. The poly(amide-imide) is represented by formula (1), wherein R is a C6 aryl group, a C7-C8 aralkyl group, a C2-C6 alkoxyalkyl group, or a C3-C18 alkyl group; and 0.02?X?0.5.
    Type: Application
    Filed: February 25, 2019
    Publication date: February 20, 2020
    Applicant: Taiwan Textile Research Institute
    Inventors: Shang-Chih Chou, Shao-Yen Chang, Chun-Hung Lin
  • Publication number: 20200051975
    Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage transistor device is disposed in a low voltage region defined on a substrate. The low voltage transistor device comprises a low voltage gate electrode and a first gate dielectric separating the low voltage gate electrode from the substrate. A high voltage transistor device is disposed in a high voltage region defined on the substrate. The high voltage transistor device comprises a high voltage gate electrode and a high voltage gate dielectric separating the high voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage transistor device and the high voltage transistor device. The high voltage gate electrode is disposed on the first interlayer dielectric layer and separated from the substrate by the first interlayer dielectric layer.
    Type: Application
    Filed: October 18, 2019
    Publication date: February 13, 2020
    Inventors: Kong-Beng Thei, Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky, Yi-Sheng Chen
  • Patent number: 10553583
    Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region, and a method of formation. In some embodiments, the integrated circuit comprises a first gate boundary dielectric layer disposed over a substrate in the low voltage region. A second gate boundary dielectric layer is disposed over the substrate in the high voltage region having a thickness greater than that of the first boundary dielectric layer. The first boundary dielectric layer meets the second boundary dielectric layer at the boundary region. A first polysilicon component is disposed within the boundary region over the first boundary dielectric layer and the second gate boundary layer. A second polysilicon component is disposed within the boundary region over the first polysilicon component. A hard mask component is disposed over the first polysilicon component and laterally neighbored to the second polysilicon component.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: February 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Kong-Beng Thei
  • Publication number: 20200027845
    Abstract: In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Kong-Beng Thei, Meng-Han Lin
  • Publication number: 20200027846
    Abstract: In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Kong-Beng Thei, Meng-Han Lin
  • Patent number: 10535752
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kong-Beng Thei, Chien-Chih Chou, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky
  • Patent number: 10520528
    Abstract: A dew resistant module for a test socket, and an electronic component testing device having the same are provided. An enclosure body is provided to circumscribe the test socket; and a test socket base plate provided on top of the test socket and enclosure body. A cover is provided to cover the test socket, enclosure body and test socket base plate. With the provision of the enclosure body and the cover, the test socket, test socket base plate and a portion of the thermal head are prevented from coming into contact directly with the atmosphere, whereby condensation or dewing is prevented, thermal insulation achieved and energy consumption minimized.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 31, 2019
    Assignee: CHROMA ATE INC.
    Inventors: Xin-Yi Wu, Chien-Hung Lo, Jui-Chih Chou, Hao-Che Yang, Nan-Yi Kuo