Patents by Inventor Chih Chou

Chih Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220367655
    Abstract: A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Kong-Beng Thei, Ming-Ta Lei, Ruey-Hsin Liu, Ta-Yuan Kung
  • Publication number: 20220367452
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate, a gate electrode, a gate dielectric layer, first protection structures, a second protection structure and an insulating layer. The gate electrode is disposed within the substrate. The gate dielectric layer is disposed within the substrate and laterally surrounds the gate electrode. The first protection structures are disposed over the gate electrode. The second protection structure is disposed over the gate dielectric layer. The insulating layer is between the second protection structure and the gate dielectric layer.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: JHU-MIN SONG, CHIEN-CHIH CHOU, KONG-BENG THEI, FU-JIER FAN
  • Publication number: 20220367709
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure disposed over the gate dielectric layer; and a pair of source/drain regions on opposing sides of the gate dielectric layer.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 17, 2022
    Inventors: YI-HUAN CHEN, CHIEN-CHIH CHOU, SZU-HSIEN LIU, KONG-BENG THEI, HUAN-CHIH YUAN, JHU-MIN SONG
  • Publication number: 20220367654
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Yi-Huan Chen, Kong-Beng Thei, Chien-Chih Chou, Alexander Kalnitsky, Szu-Hsien Liu, Huan-Chih Yuan
  • Publication number: 20220367708
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a doped region within the substrate; a pair of source/drain regions extending along a first direction on opposite sides of the doped region; a gate electrode disposed in the doped region, wherein the gate electrode has a plurality of first segments extending in parallel along the first direction; and a protection structure over the substrate and at least partially overlaps the gate electrode.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 17, 2022
    Inventors: YI-HUAN CHEN, CHIEN-CHIH CHOU, SZU-HSIEN LIU, KONG-BENG THEI
  • Patent number: 11493835
    Abstract: An elevating mechanism adapted to accommodate a function unit and including main frame, elevating frame, and accommodation frame. The main frame has first guide portion including straight portion and non-straight portion. The elevating frame is movably disposed on the main frame. The accommodation frame is pivotably connected to the elevating frame and has second guide portion slidably located at the first guide portion. When the accommodation frame is in non-inclined position, the second guide portion is located at the straight portion. When the accommodation frame is in inclined position, the second guide portion is located at the non-straight portion and the accommodation frame is inclined with respect to the main frame.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: November 8, 2022
    Assignee: WISTRON CORP.
    Inventors: Guangguo Cheng, Ai Xu, Yougang Wang, Chih Chou Chou
  • Publication number: 20220352161
    Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.
    Type: Application
    Filed: July 19, 2022
    Publication date: November 3, 2022
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Kong-Beng Thei, Ming Chyi Liu, Shih-Chung Hsiao, Jhih-Bin Chen
  • Publication number: 20220352152
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo
  • Patent number: 11486442
    Abstract: A slide rail assembly includes a first rail, a second rail, a blocking feature, and a component. The two rails can be displaced with respect to each other. The blocking feature is provided at one of the two rails, and the component at the other of the two rails. When the second rail is at a predetermined position with respect to the first rail, a blocking portion of the blocking feature and a predetermined portion of the component are blocked by each other to prevent the second rail from being displaced with respect to the first rail from the predetermined position in a predetermined direction. One of the blocking portion and the predetermined portion forms a non-vertical structure.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: November 1, 2022
    Assignees: King Slide Works Co., Ltd., King Slide Technology Co., Ltd.
    Inventors: Ken-Ching Chen, Shun-Ho Yang, Chi-Chih Chou, Chun-Chiang Wang
  • Publication number: 20220342459
    Abstract: A supporting back plate is applied to a direct back-lit display with a thin type, which includes a first casing, a second casing, an optical member, at least one circuit board, the supporting back plate and lights. The first casing has an opening portion and is connected to the second casing. The optical member is disposed between the first casing and the second casing, and exposed via the opening portion. The supporting back plate is disposed between the second casing and optical member. The supporting back plate includes a first area and a second area. A distance from the first area to the second casing is greater than a distance from the second area to the second casing. The circuit board is disposed on the first area of the supporting back plate. The lights are disposed on the supporting back plate.
    Type: Application
    Filed: July 22, 2021
    Publication date: October 27, 2022
    Applicant: Wistron Corporation
    Inventors: Yao-Chen Yang, LIANG YANG, ZHIHUA LIU, Zhiyi Liang, Chih-Chou Chou
  • Patent number: 11469307
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Kong-Beng Thei, Chien-Chih Chou, Alexander Kalnitsky, Szu-Hsien Liu, Huan-Chih Yuan
  • Publication number: 20220320384
    Abstract: A light-emitting device is applicable to a backlight module. The light-emitting device includes a substrate, a light-emitting diode (LED) and an encapsulation body. The encapsulation body is on the substrate and covers the LED. The encapsulation body includes a base and a lens. The base has a base surface. The lens has a lens surface. The lens surface conforms to a cubic Bezier curve. The cubic Bezier curve has a start point and an end point. The start point of the cubic Bezier curve is at the base surface. The end point of the cubic Bezier curve corresponds to the center of the LED. The lens surface is provided with a concave portion at the end point. The lens increases the light-emitting angle of the LED, so that the spacing between light-emitting devices can be increased, thereby reducing the number of light-emitting devices to be used and the costs.
    Type: Application
    Filed: June 8, 2021
    Publication date: October 6, 2022
    Inventors: Bin LUO, Rui-Hua WANG, Chih-Chou CHOU
  • Publication number: 20220308425
    Abstract: An elevating mechanism adapted to accommodate a function unit and including main frame, elevating frame, and accommodation frame. The main frame has first guide portion including straight portion and non-straight portion. The elevating frame is movably disposed on the main frame. The accommodation frame is pivotably connected to the elevating frame and has second guide portion slidably located at the first guide portion. When the accommodation frame is in non-inclined position, the second guide portion is located at the straight portion. When the accommodation frame is in inclined position, the second guide portion is located at the non-straight portion and the accommodation frame is inclined with respect to the main frame.
    Type: Application
    Filed: June 9, 2021
    Publication date: September 29, 2022
    Inventors: GUANGGUO CHENG, AI XU, YOUGANG WANG, CHIH CHOU CHOU
  • Patent number: 11455157
    Abstract: A display device includes a display panel, a first storage device, a second storage device and a control device. The first storage device is disposed on the display panel and stores a first firmware. The second storage device stores a second firmware. The control device is coupled to the first storage device and the second storage device. The control device reads the first firmware and uses the first firmware to update the second firmware, or receives a third firmware transmitted by a host terminal device and uses the third firmware to update the second firmware. The control device executes the updated second firmware to generate an image signal corresponding to the updated second firmware to the display panel. Therefore, the efficiency of updating the firmware of the display device may be effectively increased, and the convenience of use is increased.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: September 27, 2022
    Assignee: WISTRON CORP.
    Inventors: Li Fan Zheng, Chih Chou Chou, Su-Ming Lin, Jun Xin Qiu, Yong Qiang Li
  • Patent number: 11444169
    Abstract: A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Kong-Beng Thei, Ming-Ta Lei, Ruey-Hsin Liu, Ta-Yuan Kung
  • Patent number: 11442508
    Abstract: The present invention discloses an expansion electronic system and an electronic system. The expansion electronic device is adapted to be joined with a primary electronic device into one integral and to operate cooperatively. The expansion electronic device includes a housing and a plurality of functional modules. The housing has an assembly surface on a top side thereof and a plurality of individually independent receiving chambers on a bottom side thereof. The assembly surface is configured to join with the primary electronic device, and a first waterproof space is formed by means of structural interference between the assembly surface and the primary electronic device. The plurality of functional modules are disposed in the plurality of receiving chambers, respectively, and are individually installed or removed. A second waterproof space is formed by means of structural interference between one of the receiving chambers and the corresponding functional module.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: September 13, 2022
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventors: Hsin-Chih Chou, Juei-Chi Chang
  • Patent number: 11428986
    Abstract: A direct-type light source module including N-stage light sources and an optical sheet is provided. The optical sheet is disposed above the N-stage light sources, and an optical distance between the i-th-stage light source and the optical sheet is smaller than an optical distance between the i+1-th-stage light source and the optical sheet, where 1?i<N, and N is a positive integer greater than 1. A display device is also provided.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: August 30, 2022
    Assignee: Wistron Corporation
    Inventors: Han-Jen Liang, Lei-Ken Hung, Ching-Hsuan Tsai, Wei-Chi Lin, Chih-Chou Chou
  • Publication number: 20220271146
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.
    Type: Application
    Filed: February 9, 2022
    Publication date: August 25, 2022
    Inventors: Kong-Beng Thei, Chien-Chih Chou, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky
  • Patent number: 11410999
    Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: August 9, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Kong-Beng Thei, Ming Chyi Liu, Shih-Chung Hsiao, Jhih-Bin Chen
  • Patent number: 11410995
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a well region extending in a first direction; a gate electrode disposed within the substrate and overlapping the well region; a gate dielectric layer disposed within the substrate and laterally surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure extending in a second direction different from the first direction over the gate dielectric layer; and an insulating layer extending in the second direction between the second protection structure and the gate dielectric layer.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jhu-Min Song, Chien-Chih Chou, Kong-Beng Thei, Fu-Jier Fan