Patents by Inventor Chih-Chun Chen

Chih-Chun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11143675
    Abstract: An insulator applied in a probe base including a probe mounting hole, the insulator is a sheet structure having plural through holes, and the probe mounting hole is formed at the center of the insulator, and the probe mounting hole and the through hole penetrate from a first surface to a second surface of the insulator, and the regions of the first and second surfaces without the probe mounting hole and the through hole are coplanar. The probe base has a base body and at least a composite assembly, and the base body has at least a testing zone, and the composite assembly is installed in the testing zone and has at least a probe hole for installing a probe, and the insulator is installed into the probe hole.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 12, 2021
    Assignee: C.C.P. CONTACT PROBES CO., LTD.
    Inventors: Chien-Yu Hsieh, Yen-Chun Chen, Chih-Hui Hou, Wei-Chu Chen, Yen-Hui Lu, Ting-Chen Pan, Yen-Wei Lin, Bor-Chen Tsai
  • Patent number: 11146273
    Abstract: The present invention provides an electronic device including a wireless communication module, a counter and a processing circuit. The wireless communication module is configured to receive a first packet and a second packet from another electronic device, wherein the first packet includes a first counter value, the second packet includes a second counter value, and the first counter value and the second counter value correspond to two adjacent edges of an original signal of another electronic device, respectively. The processing circuit is configured to obtain a third counter value from the counter when the first packet is received, and obtain a fourth counter value from the counter when the second packet is received; and the processing circuit further generates an output signal that is substantially the same as the original signal according to the first counter value, the second counter value, the third counter value and the fourth counter value.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: October 12, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chia-Chun Hung, Chih-Wei Ho, Chin-Wen Wang, Liang-Hui Li, Yi-Cheng Chen
  • Publication number: 20210311105
    Abstract: A test apparatus includes a tray including at least a first region and a second region, and a cap disposed over the tray. The cap includes a cap body, and at least a first magnet and a second magnet disposed over the cap body. The first magnet is configured to provide a first magnetic field to the first region of the tray, and the second magnet is configured to provide a second magnetic field to the second region of the tray. A strength of the first magnetic field is different from a strength of the second magnetic field.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Inventors: HARRY-HAK-LAY CHUANG, TIEN-WEI CHIANG, CHIA YU WANG, MENG-CHUN SHIH, CHING-HUANG WANG, CHIH-YANG CHANG, CHIA-HSIANG CHEN, CHIH-HUI WENG
  • Patent number: 11139225
    Abstract: A device includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle, an outer lead portion opposite to the inner lead portion and a bridge portion between the inner lead portion and the outer lead portion. The inner lead portion has an upper bond section connected to the bridge portion and a lower support section below the upper bond section. A sum of a thickness of the upper bond section and a thickness of the lower support section is greater than a thickness of the bridge portion.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuang-Hsiung Chen, Chih-Hung Hsu, Mei-Lin Hsieh, Yi-Cheng Hsu, Yuan-Chun Chen, Yu-Shun Hsieh, Ko-Pu Wu
  • Patent number: 11135206
    Abstract: The present invention provides novel pyrazolo[4,3-c]quinoline derivatives exhibiting specifically inhibition activity to microbiota ?-glucuronidase, whereby providing potent activities to prevent chemotherapy-induced diarrhea (CID) of cancers. Therefore, the compounds of the present invention can be used as (1) chemotherapy-adjuvant to prevent chemotherapy-induced diarrhea (CID) and enhance chemotherapeutic efficiency of cancers; (2) health-food supplement to prevent the carcinogens induced colon carcinoma.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: October 5, 2021
    Assignee: KAOHSIUNG MEDICAL UNIVERSITY
    Inventors: Yeh-Long Chen, Tian-Lu Cheng, Cherng-Chyi Tzeng, Chih-Hua Tseng, Ta-Chun Cheng, Kai-Wen Cheng, Wei-Fen Luo
  • Patent number: 11139006
    Abstract: A self-biased sense amplification circuit includes a local bit line, a reset unit, a main bit lie, a pre-amplifier, a data line, a sample reference unit, and a sense amplifier. The local bit line receives a cell current generated by a memory cell during a sense operation. The reset unit resets the local bit line to a first system voltage during a sample operation. The pre-amplifier generates a read current on the main bit line according to a voltage of the local bit line during the sample operation and the sense operation. The data line is coupled to the main bit line. The sample reference unit generates a first reference current and a second reference current during the sample operation, and generates the first reference current during the sense operation. The sense amplifier senses a voltage of the data line.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: October 5, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Chih-Chun Chen, Chun-Hung Lin
  • Publication number: 20210286412
    Abstract: A portable electronic device including a first body, a second body, a hinge mechanism, a control unit, a sensor unit, a sterilization module, and a shielding module, is provided. The first body has a first inner surface. The second body has a second inner surface. The hinge mechanism is connected between the first body and the second body. The control unit is disposed in the first body or the second body. The sensor unit is disposed in the first body or the second body and coupled to the control unit. The sterilization module is disposed at the hinge mechanism and coupled to the control unit, the sterilization module is configured to generate light for sterilization and disinfection. The shielding module is disposed on the hinge mechanism and the shielding module can move relative to the hinge mechanism.
    Type: Application
    Filed: March 5, 2021
    Publication date: September 16, 2021
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Yi-Chun Lin, Ya-Hui Tseng, I-Kai Liu, Po-Ching Chiang, Chien-Lun Sun, Yen-Kang Chen, Jih-Houng Lee, Chih-Chien Liu
  • Publication number: 20210285107
    Abstract: In some embodiments, a semiconductor fabrication tool is provided. The semiconductor fabrication tool includes a first processing zone having a first ambient environment and a second processing zone having a second ambient environment disposed at different location inside a processing chamber. A first exhaust port and a second exhaust port are disposed in the first and second processing zones, respectively. A first exhaust pipe couples the first exhaust port to a first individual exhaust output. A second exhaust pipe couples the second exhaust port to a second individual exhaust output, where the second exhaust pipe is separate from the first exhaust pipe. A first adjustable fluid control element controls the first ambient environment. A second adjustable fluid control element controls the second ambient environment, where the first adjustable fluid control element and the second adjustable fluid control element are independently adjustable.
    Type: Application
    Filed: June 2, 2021
    Publication date: September 16, 2021
    Inventors: Chiao-Chun Hsu, Chih-Ming Chen, Chung-Yi Yu, Sheng-Hsun Lu
  • Publication number: 20210287723
    Abstract: A self-biased sense amplification circuit includes a local bit line, a reset unit, a main bit lie, a pre-amplifier, a data line, a sample reference unit, and a sense amplifier. The local bit line receives a cell current generated by a memory cell during a sense operation. The reset unit resets the local bit line to a first system voltage during a sample operation. The pre-amplifier generates a read current on the main bit line according to a voltage of the local bit line during the sample operation and the sense operation. The data line is coupled to the main bit line. The sample reference unit generates a first reference current and a second reference current during the sample operation, and generates the first reference current during the sense operation. The sense amplifier senses a voltage of the data line.
    Type: Application
    Filed: December 23, 2020
    Publication date: September 16, 2021
    Inventors: Chih-Chun Chen, Chun-Hung Lin
  • Patent number: 11121256
    Abstract: A method for forming a non-planar semiconductor device includes: forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device; depositing a dielectric region on the front side of the substrate, the dielectric region including a conductive rail buried within the dielectric region and in parallel with the fin structure; etching the dielectric region to create a first opening in the dielectric region to expose the conductive rail; depositing a plurality of conductive regions on the dielectric region, one of the conductive regions contacting the conductive rail through the first opening; etching the substrate from a backside of the substrate to form a second opening to expose the conductive rail; and filling a first conductive material into the second opening to form a through-substrate via in the substrate.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Liang Chen, Lei-Chun Chou, Jack Liu, Kam-Tou Sio, Hui-Ting Yang, Wei-Cheng Lin, Chun-Hung Liou, Jiann-Tyng Tzeng, Chew-Yuen Young
  • Patent number: 11119001
    Abstract: A machine tool health monitoring method which is to use a predetermined plurality of vibration sensors on a plurality of components of a machine tool and to drive motors of the machine tool to excite the machine tool using an electronic device while the health status of the machine tool is good, and then to perform a diagnostic process to obtain a characteristic cluster consisting of a plurality of modals, and then to define the characteristic cluster as a sample health characteristic cluster. The diagnostic process includes the procedures of vibration transmissibility obtaining, singular value decomposition, curve fitting and modal establishing. In addition, excite the machine tool and proceed the diagnosis process to obtain a current health characteristic cluster. Finally, the current health characteristic cluster is compared with the sample health characteristic cluster to judge whether the machine tool is healthy or not.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 14, 2021
    Assignees: NATIONAL CHUNG CHENG UNIVERSITY, TONGTAI MACHINE & TOOL CO., LTD.
    Inventors: Chih-Chun Cheng, Yu-Sheng Chiu, Wen-Nan Cheng, Ping-Chun Tsai, Yu-Hsin Kuo, Wei-Jen Chen, De-Shin Liu, Chen-Wei Chuang, Chih-Ta Wu, Wen-Peng Tseng, Wen-Chieh Kuo
  • Publication number: 20210280607
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang CHEN, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Publication number: 20210272876
    Abstract: A transistor heat dissipation module is adapted for at least one transistor. The transistor heat dissipation module includes a heat dissipation member and an elastic member. The heat dissipation member includes a first wall and a second wall opposite to each other and a first connecting member connected to the first wall and the second wall. An accommodating space is formed between the first wall and the second wall. The transistor is disposed in the accommodating space. The elastic member is disposed in the accommodating space and is located between the at least one transistor and the first wall to press the at least one transistor against the second wall. An assembly method of a transistor heat dissipation module is further provided.
    Type: Application
    Filed: April 20, 2020
    Publication date: September 2, 2021
    Applicants: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, Lite-On Technology Corporation
    Inventors: Cheng-Chung Chiang, Yu-Po Chen, Ping-Ho Chu, Chih-Chun Yu
  • Publication number: 20210272849
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 11107805
    Abstract: An integrated circuit includes a first cell and a second cell. The first cell with a first cell height along a first direction includes a first active region and a second active region that extend in a second direction different from the first direction. The first active region overlaps the second active region in a layout view. The second cell with a second cell height includes a first plurality of active regions and a second plurality of active regions. The first plurality of active regions and the second plurality of active regions extend in the second direction and the first plurality of active regions overlap the second plurality of active regions, respectively, in the layout view. The first cell abuts the second cell, and the first active region is aligned with one of the first plurality of active regions in the layout view.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Sing Li, Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 11106000
    Abstract: A driving mechanism for supporting an optical member is provided, including a base, a frame, a movable portion, a driving module, and an adhesive member. The base includes a plurality of first sidewalls, and at least one recess is formed on the first sidewalls. The frame includes a plurality of second sidewalls, and at least one opening is formed on the second sidewalls. The base and the frame form a hollow box, and the opening corresponds to the recess. The movable portion and the driving module are disposed in the hollow box. The driving module can drive the movable portion to move relative to the base. The adhesive member is accommodated in the opening and the recess, and extended along the first sidewalls. The adhesive member is disposed between the first sidewalls and the second sidewalls.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 31, 2021
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Patent number: 11107981
    Abstract: Disclosures of the present invention describe a halide semiconductor memristor that is suitable for being as an artificial synapse. The halide semiconductor memristor comprises a first electrode layer, an active layer and a second electrode layer, wherein the active layer comprises a first oxide semiconductor film formed on the first electrode layer, a halide semiconductor film formed on the first oxide semiconductor film, and a second oxide semiconductor film formed on the halide semiconductor film Moreover, a variety of experimental data have proved that, this halide semiconductor memristor is indeed suitable for being adopted as a plurality of artificial synapses that are used in manufacture of a neuromorphic device, and exhibits many advantages, including: capable of being driven by a low operation voltage, having a multi-stage adjustable resistance state, and a wide dynamic range of the switching resistance states.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 31, 2021
    Inventors: Hao-Wu Lin, Chien-Yu Chen, Tse-Wei Chen, Li-Wei Chen, Wei-Chun Wang, Chih-Ting Hsu
  • Publication number: 20210265998
    Abstract: The present invention provides an electronic device including a wireless communication module, a counter and a processing circuit. The wireless communication module is configured to receive a first packet and a second packet from another electronic device, wherein the first packet includes a first counter value, the second packet includes a second counter value, and the first counter value and the second counter value correspond to two adjacent edges of an original signal of another electronic device, respectively. The processing circuit is configured to obtain a third counter value from the counter when the first packet is received, and obtain a fourth counter value from the counter when the second packet is received; and the processing circuit further generates an output signal that is substantially the same as the original signal according to the first counter value, the second counter value, the third counter value and the fourth counter value.
    Type: Application
    Filed: February 22, 2021
    Publication date: August 26, 2021
    Inventors: Chia-Chun Hung, Chih-Wei Ho, Chin-Wen Wang, Liang-Hui Li, Yi-Cheng Chen
  • Patent number: 11063389
    Abstract: A connector structure includes a first connector and a second connector configured to rotatably connect the first connector. The first connector includes an insulating support, a first conductor and a second conductor. The first and second conductors respectively include first and second convex curved surfaces. The second connector includes first and second insulating housings and first and second conductive layers. The first and second insulating housings are configured to cover at least a portion of the first conductor and at least a portion of the second conductor, respectively. The first conductive layer includes a first concave curved surface matching the first convex curved surface, and is configured to be in contact with the first conductor. The second conductive layer includes a second concave curved surface matching the second convex curved surface, and is configured to be in contact with the second conductor.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: July 13, 2021
    Assignee: E Ink Holdings Inc.
    Inventors: Huei-Chuan Lee, Yen-Ze Huang, Chih-Chun Chen, Chin-Chi Yu
  • Patent number: 11042071
    Abstract: A waterproof display apparatus includes a bottom waterproof structure, a plurality of driving substrates, a panel laminate (FPL) and a top waterproof structure. The bottom waterproof structure has a first edge. The driving substrates are disposed on the bottom waterproof structure and defining a gap between adjacent driving substrates. The gap has opposite top and bottom portions. The FPL covers the driving substrates and includes a display medium layer therein. The top waterproof structure covers the FPL and has a second edge. The first and second edges are joined in a waterproof manner. The bottom portion of the gap is sealed by the bottom waterproof structure, and the top portion of the gap is sealed by the FPL or the top waterproof structure such that the gap is empty.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: June 22, 2021
    Assignee: E Ink Holdings Inc.
    Inventors: Chin-Chi Yu, Chih-Chun Chen, Shi-Lin Li, Hsin-Chung Wu