Patents by Inventor Chih-Chun Chen

Chih-Chun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220310584
    Abstract: A semiconductor cell structure includes first-type transistors aligned within a first-type active zone, second-type transistors aligned within a second-type active zone, a first power rail and a second power rail. Each of the first-type active zone and the second-type active zone is between a first alignment boundary and a second alignment boundary extending in a first direction which is perpendicular to a second direction. A first distance along the second direction between the long edge of the first power rail and the first alignment boundary of the first-type active zone is different from a second distance along the second direction between the long edge of the second power rail and the first alignment boundary of the second-type active zone by a predetermined distance.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: Guo-Huei WU, Chih-Liang CHEN, Li-Chun TIEN
  • Publication number: 20220310598
    Abstract: A semiconductor device includes a buried communication (com) conductor (BC) CFET including: first and second active regions arranged in a stack according to CFET-type configuration; a first layer of metallization (M_1st layer) over the stack which includes first conductors configured for data or control signals (communication (com) conductors), and power grid (PG) conductors; and a layer of metallization (M_B layer) below the stack and which includes second com conductors.
    Type: Application
    Filed: June 14, 2022
    Publication date: September 29, 2022
    Inventors: Guo-Huei Wu, Pochun Wang, Chih-Liang Chen, Li-Chun Tien
  • Publication number: 20220311357
    Abstract: In some embodiments, the present disclosure relates to a microelectromechanical system (MEMS) comb actuator including a comb structure. The comb structure includes a support layer having a first material and a plurality of protrusions extending away from a first surface of the support layer in a first direction. The plurality of protrusions are also made of the first material. The plurality of protrusions are separated along a second direction parallel to the first surface of the support layer. The MEMS comb actuator may further include a dielectric liner structure that continuously and completely covers the first surface of the support layer and outer surfaces of the plurality of protrusions. The dielectric liner structure includes a connective portion that continuously connects topmost surfaces of at least two of the plurality of protrusions.
    Type: Application
    Filed: June 16, 2022
    Publication date: September 29, 2022
    Inventors: Chiao-Chun Hsu, Chih-Ming Chen, Chung-Yi Yu, Lung Yuan Pan
  • Publication number: 20220299625
    Abstract: A range Doppler angle detection method executed by a range Doppler angle detection device includes steps of: receiving a first sensing signal and a second sensing signal; performing 1D Fast Fourier Transform (FFT) and 2D FFT to the first sensing signal for calculating one first 2D FFT map; performing the 1D FFT and the 2D FFT to the second sensing signal for calculating one second 2D FFT map; picking up one column of the first 2D FFT map and one column of the second 2D FFT map according to a given Doppler index; performing the 3D FFT to the picked column of the first 2D FFT map and the picked column of the second 2D FFT map for calculating a range Doppler angle. Therefore, a computation loading of the gesture recognition function can be reduced.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Inventors: Mike Chun-Hung Wang, Chun-Hsuan Kuo, Chih-Wei Chen, Wen-Sheng Cheng, Guan-Sian Wu, Chieh Wu, Wen-Jyi Hwang, Yu-Feng Wu, Khoi Duc Le
  • Publication number: 20220302111
    Abstract: A method is provided and includes operations below: forming a multilayer stack, wherein the multilayer stack includes multiple first semiconductor layers and multiple second semiconductor layers that are alternately stacked; forming a first source region and a first drain region on opposing sides of a first portion of the multilayer stack and forming a second source region and a second drain region on opposing sides of a second portion of the multilayer stack; removing the second semiconductor layers in the multilayer stack; forming a first gate region, corresponding to a first transistor, over the first portion of the multilayer stack; forming a first insulating layer above the first gate region; and forming a second gate region, corresponding to a second transistor, above the first insulating layer and over the second portion of the multilayer stack.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guo-Huei WU, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
  • Patent number: 11450596
    Abstract: A lead frame includes a die paddle, a plurality of leads, at least one connector and a bonding layer. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle and an outer lead portion opposite to the inner lead portion. The connector is connected to the die paddle and the inner lead portions of the leads. The bonding layer is disposed on a lower surface of the die paddle and a lower surface of each of the outer lead portions.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: September 20, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yi-Cheng Hsu, Chih-Hung Hsu, Mei-Lin Hsieh, Yuan-Chun Chen, Yu-Shun Hsieh, Ko-Pu Wu, Chin Li Huang
  • Publication number: 20220293638
    Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.
    Type: Application
    Filed: May 31, 2022
    Publication date: September 15, 2022
    Inventors: POCHUN WANG, GUO-HUEI WU, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN, LI-CHUN TIEN
  • Patent number: 11444071
    Abstract: An integrated circuit disclosed here includes several cell rows extending in a first direction and a multi-bit cell having several bit cells included in the cell rows. The bit cells include M bit cells, and an output signal of a N-th bit cell of the M bit cells is an input signal of a (N+1)-th bit cell of the M bit cells, N and M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell, and the N-th bit cell and the (N+1)-th bit cell are arranged diagonally in different cell rows in the multi-bit cell.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Lun Chien, Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 11443095
    Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Shuo Liu, Chih-Chun Hsia, Hsin Ting Chou, Kuanhua Su, William Weilun Hong, Chih Hung Chen, Kei-Wei Chen
  • Publication number: 20220285600
    Abstract: A micro light emitting device display apparatus including a substrate, a plurality of micro light emitting devices, an isolation layer, and at least one first air gap is provided. The substrate has a plurality of connection pads. The micro light emitting devices are discretely disposed on the substrate. The isolation layer is disposed between the substrate and each of the micro light emitting devices. The at least one first air gap is disposed between the substrate and a surface of the isolation layer facing the substrate.
    Type: Application
    Filed: May 16, 2022
    Publication date: September 8, 2022
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Chih-Ling Wu, Yen-Yeh Chen, Yi-Min Su, Yi-Chun Shih
  • Publication number: 20220278091
    Abstract: A semiconductor structure including first finfet cells and second finfet cells. Each of the first finfet cells has an analog fin boundary according to analog circuit design rules, and each of the second finfet cells has a digital fin boundary according to digital circuit design rules. The semiconductor structure further includes first circuits formed with the first finfet cells, second circuits formed with the second finfet cells, and third circuits formed with one or more of the first finfet cells and one or more of the second finfet cells.
    Type: Application
    Filed: December 6, 2021
    Publication date: September 1, 2022
    Inventors: Chung-Hui Chen, Weichih Chen, Tien-Chien Huang, Chien-Chun Tsai, Ruey-Bin Sheen, Tsung-Hsin Yu, Chih-Hsien Chang, Cheng-Hsiang Hsieh
  • Publication number: 20220277985
    Abstract: A method includes, through a backside of a substrate, removing a portion of a gate structure to form a trench that isolates the gate structure in two portions. The method further includes depositing a sacrificial material within the trench and conformally along sidewalls of the trench, filling a remainder of the trench with a first dielectric material, partially removing the sacrificial material to leave an opening between the first dielectric material and the gate structure, and filling the opening with a work-function metal.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Wang-Chun Huang, Yu-Xuan Huang, Hou-Yu Chen, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11430916
    Abstract: A light-emitting device comprises a semiconductor layer; a pad electrode comprising a periphery disposed on the semiconductor layer; a finger electrode connected to the pad electrode, wherein the finger electrode comprises a first portion extended from the periphery of the pad electrode and a second portion connected to the first portion; and a plurality of first current blocking regions formed on the semiconductor layer, separated from the pad electrode and formed under the finger electrode, wherein one of the plurality of first current blocking regions is most close to the pad electrode and is separated from the pad electrode by a first distance, adjacent two of others of the plurality of first current blocking regions are separated from each other by a second distance, and the first distance is longer than the second distance.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: August 30, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Chien-Hua Chou, Tai-Chun Wang, Chih-Tsung Su, Biau-Dar Chen
  • Patent number: 11429150
    Abstract: An electronic device, including a host, a main display, an auxiliary display, and a lifting mechanism, is provided. The main display is pivoted to the host. The auxiliary display is disposed on the host. The lifting mechanism is disposed between the auxiliary display and the host. The lifting mechanism is configured to lift the auxiliary display and maintain a lifting height of the auxiliary display.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: August 30, 2022
    Assignee: Acer Incorporated
    Inventors: Chia-Bo Chen, Yi-Hsuan Yang, Chuan-Hua Wang, Chih-Chun Liu, Wu-Chen Lee
  • Publication number: 20220269467
    Abstract: An image displaying device includes a planar display panel and a light penetrating unit. The planar display panel displays a plane image. The planar display panel at least includes a first pixel group, a second pixel group and a third pixel group. The second pixel group is located between the first pixel group and the third pixel group. When vision passes through the light penetrating unit toward the planar display panel, the vision acquires a second distance of a second imaging position within the plane image relevant to the second pixel group relative to the planar display panel being greater than a first distance of a first imaging position within the plane image relevant to the first pixel group relative to the planar display panel and a third distance of a third imaging position within the plane image relevant to the third pixel group relative to the planar display panel.
    Type: Application
    Filed: January 10, 2022
    Publication date: August 25, 2022
    Applicant: QISDA CORPORATION
    Inventors: Hao-Chun Tung, Hsin-Che Hsieh, Wei-Jou Chen, Po-Fu Wu, Yu-Fu Fan, Chih-Ming Chang
  • Patent number: 11422330
    Abstract: A driving mechanism for moving an optical element is provided, including a movable portion, a fixed portion, a driving assembly, and a first resilient element. The movable portion is for connecting the optical element. The movable portion is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion. The first resilient element has a board structure. The movable portion is movably connected to the fixed portion via the first resilient element. The fixed portion includes a connection surface, a restricting surface, and a recessed portion. At least a portion of the first resilient element is disposed on the connection surface. The restricting surface contacts and restricts the movable portion. The recessed portion is located between the connection surface and the restricting surface, wherein the recessed portion is lower than the connection surface and the restricting surface.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: August 23, 2022
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Patent number: D962221
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: August 30, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chee-Chun Leung, Wen-Hung Tsai, Chang-Ta Miao, Gwo-Chyuan Chen, Chih-Kang Ting, Shun-Kai Chuang
  • Patent number: D962222
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: August 30, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chee-Chun Leung, Wen-Hung Tsai, Chang-Ta Miao, Gwo-Chyuan Chen, Chih-Kang Ting, Shun-Kai Chuang
  • Patent number: D962223
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: August 30, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chee-Chun Leung, Wen-Hung Tsai, Chang-Ta Miao, Gwo-Chyuan Chen, Chih-Kang Ting, Shun-Kai Chuang
  • Patent number: D962921
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: September 6, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chee-Chun Leung, Wen-Hung Tsai, Chang-Ta Miao, Gwo-Chyuan Chen, Chih-Kang Ting, Shun-Kai Chuang