Patents by Inventor Chih-Chun Chen
Chih-Chun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10176883Abstract: A power-up sequence protection circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. First terminals of the first transistor, the second transistor, and the fourth transistor are coupled for receiving a program voltage. A control terminal of the third transistor is used for receiving a device voltage. A second terminal of the fourth transistor is used for outputting the program voltage when the fourth transistor is turned on. When the program voltage is unexpectedly powered up while the device voltage is not powered up, the first transistor is turned on, the second transistor is turned off, and the fourth transistor is turned off so as to block the program voltage outputted from the second terminal of the fourth transistor.Type: GrantFiled: January 10, 2017Date of Patent: January 8, 2019Assignee: eMemory Technology Inc.Inventors: Chieh-Tse Lee, Chih-Chun Chen, Cheng-Da Huang, Chun-Hung Lin
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Publication number: 20180315482Abstract: A sensing circuit includes a sensing stage. The sensing stage includes a voltage clamp, a P-type transistor and an N-type transistor. The voltage clamp receives a first power supply voltage and generates a second power supply voltage. The source terminal of the P-type transistor receives the second power supply voltage. The gate terminal of the P-type transistor receives a cell current from a selected circuit of a non-volatile memory. The drain terminal of the N-type transistor is connected with the drain terminal of the P-type transistor. The gate terminal of the N-type transistor receives a bias voltage. The source terminal of the N-type transistor receives a ground voltage. In a sensing period, the second power supply voltage from the voltage clamp is fixed and lower than the first power supply voltage.Type: ApplicationFiled: April 2, 2018Publication date: November 1, 2018Inventors: Chih-Chun CHEN, Chun-Hung Lin, Cheng-Da Huang
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Patent number: 10111315Abstract: An arc suppression device includes an AC to DC converter, a switch, a resistor and a controller. The switch is coupled between the AC to DC converter and a plasma chamber. The resistor is coupled in parallel with the switch. The AC to DC converter is configured to convert an AC voltage into a DC voltage for providing to the plasma chamber. The controller is configured to detect a unit-time rate of change (ROC) of a plasma current received by the plasma chamber. When the controller determines that the unit-time ROC of the plasma current is larger than a first unit-time ROC threshold, the controller controls the switch to electrically isolate the AC to DC converter and the plasma chamber to reduce the plasma current to a first current value through the resistor.Type: GrantFiled: November 13, 2017Date of Patent: October 23, 2018Assignee: DELTA ELECTRONICS, INC.Inventors: Wei-Hsun Lai, Chien-Yu Wang, Po-Cheng Chiu, Chih-Chun Chen
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Patent number: 10094717Abstract: A thermal sensing device comprises a substrate, a first insulating layer, at least one first sensing resistor, at least one second sensing resistor, a plurality of etching holes and a cavity. The first insulating layer is disposed on the substrate. The first sensing resistor is disposed above the first insulating layer. The second sensing resistor is disposed above the first insulating layer and isolated from the at least one first sensing resistor. The etching holes are disposed around the at least one first sensing resistor and the at least one second sensing resistor. The cavity is formed below the at least one first sensing resistor and the at least one second sensing resistor. The thermal sensing device is implemented in a measurement circuit to improve the problem that the signal becomes smaller when the sensing element is minimized.Type: GrantFiled: December 22, 2015Date of Patent: October 9, 2018Assignee: NATIONAL KAOHSIUNG UNIVERSITY OF APPLIED SCIENCESInventors: Chung-Nan Chen, Chih-Chun Chen, Chun-Hao Chen, Wen-Chie Huang
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Publication number: 20180095309Abstract: A waterproof display apparatus includes a bottom waterproof structure, a plurality of driving substrates, a panel laminate (FPL) and a top waterproof structure. The bottom waterproof structure has a first edge. The driving substrates are disposed on the bottom waterproof structure and defining a gap between adjacent driving substrates. The gap has opposite top and bottom portions. The FPL covers the driving substrates and includes a display medium layer therein. The top waterproof structure covers the FPL and has a second edge. The first and second edges are joined in a waterproof manner. The bottom portion of the gap is sealed by the bottom waterproof structure, and the top portion of the gap is sealed by the FPL or the top waterproof structure such that the gap is empty.Type: ApplicationFiled: May 11, 2017Publication date: April 5, 2018Inventors: Chin-Chi YU, Chih-Chun CHEN, Shi-Lin LI, Hsin-Chung WU
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Patent number: 9853832Abstract: The present disclosure provides a wireless Ethernet network controlling method, for connecting a mobile device to an Ethernet through a wireless dock, comprising: connecting an Ethernet PHY of a wireless dock to an Ethernet; wirelessly linking a first wireless NIC of the wireless dock to a second wireless NIC of a mobile device; a control server unit of the wireless dock receiving an operation status setting signal through the first wireless NIC generated by a virtual Ethernet NIC, and the control server unit transmitting the operation status setting signal to the Ethernet PHY for setting-up the operation status of the Ethernet PHY; and a VLAN unit processing the data packets transmitted between the Ethernet PHY and the first wireless NIC. Accordingly, the user of the mobile device can experience the complete functions of the Ethernet device.Type: GrantFiled: March 17, 2015Date of Patent: December 26, 2017Assignee: UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD.Inventors: Chih-Chun Chen, Yi-Chun Lo
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Patent number: 9792968Abstract: A self-timed reset pulse generator includes a flip-flop, a tracking block, and a tracking circuit. The flip-flop receives an input signal and a feedback signal and outputting a reset signal. The tracking block has replicating cells coupled in series and replicates a structure in an external device. The tracking block has a first terminal and a second terminal. The first terminal and the second terminal are taking from the tracking block at a same location or two different locations. The tracking circuit unit receives the reset signal and receives the first terminal and the second terminal for respectively discharging the tracking block at the first terminal and sensing a voltage level at the second terminal as triggered by the reset signal. A track-out signal serving as the feed back signal is output to the flip-flop when the voltage level is less than or equal to a threshold.Type: GrantFiled: January 16, 2017Date of Patent: October 17, 2017Assignee: eMemory Technology Inc.Inventors: Chih-Chun Chen, Chun-Hung Lin, Cheng-Da Huang
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Publication number: 20170268951Abstract: A thermal type vacuum gauge is disclosed herein and includes a first floating structure, a second floating structure, a first cavity and a second cavity. The first floating structure is formed by the first insulating layer, the second insulating layer, and the first sensing resistor. The second floating structure is formed by the second insulating layer, and the second sensing resistor. The first cavity and the second cavity are respectively formed below the first floating structure and the second floating structure. The thermal type vacuum gauge is implemented in a measurement circuit having a first resistor, a second resistor, a third resistor and a fourth resistor. The first sensing resistor and the second sensing resistor are respectively implemented to be as at least two of the first resistor, the second resistor, the third resistor and the fourth resistor of the measurement circuit.Type: ApplicationFiled: March 15, 2016Publication date: September 21, 2017Inventors: Chung-Nan Chen, Chih-Chun Chen
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Publication number: 20170207773Abstract: A power-up sequence protection circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. First terminals of the first transistor, the second transistor, and the fourth transistor are coupled for receiving a program voltage. A control terminal of the third transistor is used for receiving a device voltage. A second terminal of the fourth transistor is used for outputting the program voltage when the fourth transistor is turned on. When the program voltage is unexpectedly powered up while the device voltage is not powered up, the first transistor is turned on, the second transistor is turned off, and the fourth transistor is turned off so as to block the program voltage outputted from the second terminal of the fourth transistor.Type: ApplicationFiled: January 10, 2017Publication date: July 20, 2017Inventors: Chieh-Tse Lee, Chih-Chun Chen, Cheng-Da Huang, Chun-Hung Lin
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Publication number: 20170206946Abstract: A self-timed reset pulse generator includes a flip-flop, a tracking block, and a tracking circuit. The flip-flop receives an input signal and a feedback signal and outputting a reset signal. The tracking block has replicating cells coupled in series and replicates a structure in an external device. The tracking block has a first terminal and a second terminal. The first terminal and the second terminal are taking from the tracking block at a same location or two different locations. The tracking circuit unit receives the reset signal and receives the first terminal and the second terminal for respectively discharging the tracking block at the first terminal and sensing a voltage level at the second terminal as triggered by the reset signal. A track-out signal serving as the feed back signal is output to the flip-flop when the voltage level is less than or equal to a threshold.Type: ApplicationFiled: January 16, 2017Publication date: July 20, 2017Applicant: eMemory Technology Inc.Inventors: Chih-Chun Chen, Chun-Hung Lin, Cheng-Da Huang
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Publication number: 20170176263Abstract: A thermal sensing device comprises a substrate, a first insulating layer, at least one first sensing resistor, at least one second sensing resistor, a plurality of etching holes and a cavity. The first insulating layer is disposed on the substrate. The first sensing resistor is disposed above the first insulating layer. The second sensing resistor is disposed above the first insulating layer and isolated from the at least one first sensing resistor. The etching holes are disposed around the at least one first sensing resistor and the at least one second sensing resistor. The cavity is formed below the at least one first sensing resistor and the at least one second sensing resistor. The thermal sensing device is implemented in a measurement circuit to improve the problem that the signal becomes smaller when the sensing element is minimized.Type: ApplicationFiled: December 22, 2015Publication date: June 22, 2017Applicant: NATIONAL KAOHSIUNG UNIVERSITY OF APPLIED SCIENCESInventors: Chung-Nan Chen, Chih-Chun Chen, Chun-Hao Chen, Wen-Chie Huang
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Publication number: 20170105304Abstract: A waterproof display apparatus includes an envelope, a display panel and an adhesive structure. The envelope includes an inner enclosing surface. The inner enclosing surface defines an accommodating space. The display panel is at least partially accommodated in the accommodating space of the envelope. The envelope includes a light permeable portion that allows light from the display panel to travel out of the envelope. The adhesive structure is located in the accommodating space. The adhesive structure is adhered between the inner enclosing surface of the envelope and the display panel.Type: ApplicationFiled: July 19, 2016Publication date: April 13, 2017Inventors: Chin-Chi YU, Chih-Chun CHEN, Shi-Lin LI, Hsin-Chung WU
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Patent number: 9460797Abstract: The invention provides a non-volatile memory cell structure and non-volatile memory apparatus using the same. The non-volatile memory cell structure includes a substrate, first to three wells and first to three transistors. The first to three wells are disposed in the substrate, and the first to three transistors are respectively forming on the first to three wells. The first to third transistors are coupled in series. Wherein, a control end of the first transistor is floated, a control end of the second transistor receives a bias voltage, and a control end of the third transistor is coupled to a word line signal. Moreover, the third well and the second cell are in same type, and the type of the first well is complementary to a type of the third well.Type: GrantFiled: January 27, 2015Date of Patent: October 4, 2016Assignee: eMemory Technology Inc.Inventors: Chih-Chun Chen, Chun-Hung Lin, Cheng-Da Huang
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Publication number: 20160212772Abstract: The present disclosure provides a wireless Ethernet network controlling method, for connecting a mobile device to an Ethernet through a wireless dock, comprising: connecting an Ethernet PHY of a wireless dock to an Ethernet; wirelessly linking a first wireless NIC of the wireless dock to a second wireless NIC of a mobile device; a control server unit of the wireless dock receiving an operation status setting signal through the first wireless NIC generated by a virtual Ethernet NIC, and the control server unit transmitting the operation status setting signal to the Ethernet PHY for setting-up the operation status of the Ethernet PHY; and a VLAN unit processing the data packets transmitted between the Ethernet PHY and the first wireless NIC. Accordingly, the user of the mobile device can experience the complete functions of the Ethernet device.Type: ApplicationFiled: March 17, 2015Publication date: July 21, 2016Inventors: CHIH-CHUN CHEN, YI-CHUN LO
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Publication number: 20160104534Abstract: The invention provides a non-volatile memory cell structure and non-volatile memory apparatus using the same. The non-volatile memory cell structure includes a substrate, first to three wells and first to three transistors. The first to three wells are disposed in the substrate, and the first to three transistors are respectively forming on the first to three wells. The first to third transistors are coupled in series. Wherein, a control end of the first transistor is floated, a control end of the second transistor receives a bias voltage, and a control end of the third transistor is coupled to a word line signal. Moreover, the third well and the second cell are in same type, and the type of the first well is complementary to a type of the third well.Type: ApplicationFiled: January 27, 2015Publication date: April 14, 2016Inventors: Chih-Chun Chen, Chun-Hung Lin, Cheng-Da Huang
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Publication number: 20140128147Abstract: A method for performing an online multilevel tournament duel game between players. The method includes the step of checking whether a player has bought a preset function, wherein the preset function enables the player to preset a plurality of game policies into a network game server and enter the duel game with the plurality of game policies. If yes, an account of the player logins the duel game automatically. Then, it is checked if an opponent player is available on a lowest game level. If with the preset function, one of three duel symbols is automatically selected with one of the plurality of game policies within the preset timeframe. The method further includes the step of comparing the selected duel symbols of the players when the preset timeframe has passed to determine a duel match winner.Type: ApplicationFiled: November 5, 2012Publication date: May 8, 2014Inventors: Chin Feng YU CHENG, Chih-Chun CHEN
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Tracking servo and method for tracking optical disc and optical disc device using the tracking servo
Patent number: 8432774Abstract: A tracking method executed by an optical disc device. The optical disc device includes an optical head for emitting light to read or write data from or to an optical disc. The tracking method includes steps of: providing a table for listing a plurality of predetermined track classes, and a plurality of tracking errors; calculating the number of tracks between a current track in which the optical head is currently positioned and a target track from or to which the optical head reads or writes data; determining whether the number of tracks reaches a predetermined number; searching the table for the corresponding tracking errors when the number of tracking error reaches a predetermined number; calculating second jumping tracks based on the first jumping tracks and the found tracking errors; and driving the optical head to move to the second jumping tracks for tracking.Type: GrantFiled: September 29, 2012Date of Patent: April 30, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Ying-Liang Liao, Chih-Chun Chen, Chih-Lung Hsieh -
Patent number: 8366885Abstract: A water body self-generating electrolytic reduction module is applied to a water body containing oxidizing substances. The water body self-generating electrolytic reduction module includes a self-generating unit and an electrolysis unit. The self-generating unit is coupled to the electrolysis unit. When circulating in a water transmission pipeline, the water body drives the self-generating unit to generate an electric power and deliver the electric power to the electrolysis unit. Upon receiving the electric power, the electrolysis unit performs electrolysis on the water body circulating to the electrolysis unit, so that a reduction reaction occurs to the oxidizing substances in the water body.Type: GrantFiled: August 26, 2010Date of Patent: February 5, 2013Assignee: Industrial Technology Research InstituteInventors: Chen Pang Liu, Teh Ming Liang, Bor Yu Hu, Chih Chun Chen, Dong Yuan Lin, Wen Ping Lien, Bo Yin Chu
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Patent number: 8355087Abstract: A pixel array substrate includes a substrate having a display region and a non-display region, a pixel array in the display region, first and second lead lines, first pads in the non-display region, second pads in the non-display region and on a first insulating layer, and the first insulating layer. The first lead lines electrically connect the pixel array and extend from the display region to the non-display region. Each first pad electrically connects one corresponding first lead line. The first insulating layer covers the first lead lines and exposes the first pads. The second lead lines on the first insulating layer electrically connect the pixel array and extend from the display region to the non-display region. Each second pad electrically connects one corresponding second lead line. A distance between each first pad and the adjacent second pad along a horizontal direction is 10 um˜20 um.Type: GrantFiled: December 1, 2010Date of Patent: January 15, 2013Assignee: Au Optronics CorporationInventors: Tsai-Chi Yeh, Chih-Chun Chen, Wen-Hui Peng, Ting-Shiun Huang, Sheng-Yun Hsu
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Publication number: 20120044432Abstract: A pixel array substrate includes a substrate having a display region and a non-display region, a pixel array in the display region, first and second lead lines, first pads in the non-display region, second pads in the non-display region and on a first insulating layer, and the first insulating layer. The first lead lines electrically connect the pixel array and extend from the display region to the non-display region. Each first pad electrically connects one corresponding first lead line. The first insulating layer covers the first lead lines and exposes the first pads. The second lead lines on the first insulating layer electrically connect the pixel array and extend from the display region to the non-display region. Each second pad electrically connects one corresponding second lead line. A distance between each first pad and the adjacent second pad along a horizontal direction is 10 um˜20 um.Type: ApplicationFiled: December 1, 2010Publication date: February 23, 2012Applicant: AU OPTRONICS CORPORATIONInventors: Tsai-Chi Yeh, Chih-Chun Chen, Wen-Hui Peng, Ting-Shiun Huang, Sheng-Yun Hsu