Abstract: A light-emitting device includes a first semiconductor layer; a plurality of semiconductor pillars separated from each other and formed on the first semiconductor layer, the plurality of semiconductor pillars respectively includes a second semiconductor layer and an active layer; a first electrode covering one portion of the plurality of semiconductor pillars; and a second electrode covering another portion of the plurality of semiconductor pillars, wherein the plurality of semiconductor pillars under a covering region of the first electrode are separated from each other by a first space, the plurality of semiconductor pillars outside the covering region of the first electrode are separated from each other by a second space, and the first space is larger than the second space.

Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes utilize uses of a multi-layer structure disposed on a pattern defining layer. In some embodiments, a method of fabricating a semiconductor structure includes forming a first multi-layer structure on a pattern defining layer disposed on a film stack on a substrate, patterning the first multi-layer structure to form an aperture in the first multi-layer structure, forming a first cut opening in the pattern defining layer through the aperture defined by the first multi-layer structure, and forming a second multi-layer structure on the pattern defining layer, a portion of the second multi-layer structure being disposed in the first cut opening.

Abstract: Methods for patterning in a semiconductor process are described. A dummy layer is formed having a cut therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the cut. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. Thereafter, a second pattern in the first sacrificial layer is formed comprising altering a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned. Mask portions are formed along respective sidewalls of the patterned dummy layer. The mask portions are used to form a mask.

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, and forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, where in a plan view a major axis of the opening extends in a direction that is perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form second openings in the target layer, and filling the second openings in the target layer with a conductive material.

Abstract: An illumination assembly includes a substrate, a wiring structure, a reflecting layer and a plurality of light-emitting diodes. The wiring structure is formed on a part of the substrate, and includes a catalyst layer covering the part of the substrate, and a conducting layer formed on the catalyst layer. The reflecting layer is formed on another part of the substrate that is exposed from the wiring structure. The light-emitting diodes are disposed on the wiring structure and are electrically connected to the wiring structure.

Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes utilize uses of a multi-layer structure disposed on a pattern defining layer. In some embodiments, a method of fabricating a semiconductor structure includes forming a first multi-layer structure on a pattern defining layer disposed on a film stack on a substrate, patterning the first multi-layer structure to form an aperture in the first multi-layer structure, forming a first cut opening in the pattern defining layer through the aperture defined by the first multi-layer structure, and forming a second multi-layer structure on the pattern defining layer, a portion of the second multi-layer structure being disposed in the first cut opening.

Abstract: A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.

Abstract: Provided is an electrostatic discharge protection device including a first work area and a second work area. The first work area is configured to form a face-to-face connected diode string. The first work area includes a plurality of first sub-work areas. Each of the first sub-work areas includes a first doped region of a first conductivity type disposed in a substrate, a second doped region of a second conductivity type disposed in the substrate and surrounding the first doped region, and a third doped region of the second conductivity type disposed below the second doped region. The second work area is configured to form at least one diode. The second work area includes at least one second sub-work area. The second sub-work area includes a fourth doped region of the second conductivity type disposed in the substrate. Besides, the fourth doped region is electrically connected to the first doped region.

Abstract: A transient voltage suppression device including a substrate and a first transient voltage suppressor is provided. The substrate includes a device region and a seal-ring region. The seal-ring region surrounds the device region. A first transient voltage suppressor is located in the device region. The first transient voltage suppressor includes a first well region having a first conductivity type, a first doped region having a second conductivity type, and a second doped region having the second conductivity type. The first well region is located in the substrate of the device region. The first doped region is located in the first well region. The second doped region is located in the first well region. A third doped region having the second conductivity type is located in the substrate of the seal-ring region, and the third doped region is electrically connected to the first doped region.

Abstract: An erasing method used in a flash memory comprising at least one memory block divided into a plurality of memory sectors is illustrated. Whether the memory block or the memory sector corresponding to an address has at least one under-erased transistor memory cell according to a sector enable signal is verified, wherein the sector enable signal is determined according to whether the memory block has at least one over-erased transistor memory cell. The transistor memory cells of the memory block or the memory sector will be erased according to the sector enable signal if the memory block or the memory sector corresponding to the address has the under-erased transistor memory cell.

Abstract: Methods for patterning in a semiconductor process are described. A dummy layer is formed having a cut therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the cut. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. Thereafter, a second pattern in the first sacrificial layer is formed comprising altering a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned. Mask portions are formed along respective sidewalls of the patterned dummy layer. The mask portions are used to form a mask.

Abstract: Systems and methods for a hack-proof security keyboard are described. In some embodiments, a keyboard module may include a first circuit configured to detect activation of a plurality of keys and a second circuit configured to detect activation of a subset of the plurality of keys, where the second circuit overlies the first circuit. In other embodiments, a method may include detecting an electrical signal received from a secondary membrane of a keyboard, where the keyboard includes a primary membrane configured to detect individual activation of any of a plurality of keys, and where the secondary membrane is configured to output the electrical signal in response to concurrent activation of a subset of the plurality of keys. The method may also include performing a selected action in response to the detection.

Abstract: A method of forming a patterned metal unit on an article. The method includes the steps of: providing an article that has an insulating surface; transferring a catalyst layer onto the insulating surface of the article, the catalyst layer including a catalytic material; removing a part of the catalyst layer to form a patterned catalyst layer; and forming a patterned metal layer on the patterned catalyst layer by an electroless plating technique to obtain a patterned metal unit that is constituted by the patterned catalyst layer and the patterned metal layer.

Abstract: An erasing method used in a flash memory comprising at least one memory block divided into a plurality of memory sectors is illustrated. Whether the memory block or the memory sector corresponding to an address has at least one under-erased transistor memory cell according to a sector enable signal is verified, wherein the sector enable signal is determined according to whether the memory block has at least one over-erased transistor memory cell. The transistor memory cells of the memory block or the memory sector will be erased according to the sector enable signal if the memory block or the memory sector corresponding to the address that has the under-erased transistor memory cell.

Abstract: An illumination assembly includes a substrate, a wiring structure, a reflecting layer and a plurality of light-emitting diodes. The wiring structure is formed on a part of the substrate, and includes a catalyst layer covering the part of the substrate, and a conducting layer formed on the catalyst layer. The reflecting layer is formed on another part of the substrate that is exposed from the wiring structure. The light-emitting diodes are disposed on the wiring structure and are electrically connected to the wiring structure.

Abstract: An erasing method used in a flash memory comprising at least one memory block divided into a plurality of memory sectors is illustrated. Whether the memory block or the memory sector corresponding to an address has at least one under-erased transistor memory cell according to a sector enable signal is verified, wherein the sector enable signal is determined according to whether the memory block has at least one over-erased transistor memory cell. The transistor memory cells of the memory block or the memory sector will be erased according to the sector enable signal if the memory block or the memory sector corresponding to the address that has the under-erased transistor memory cell.

Abstract: The present invention provides a primer set and a kit containing same for analyzing a sequence of an MLH1 DNA, an MLH1 mRNA, and/or a cDNA sequence derived from said MLH1 mRNA of a subject to identify a V384 alteration of an MLH1 gene encoded protein.

Abstract: A light-emitting element, includes a substrate; and a semiconductor stack formed on the substrate, including: a first semiconductor layer having a first conductivity type; a second semiconductor layer having a second conductivity type; and a light-emitting stack formed between the first and second semiconductor layers; wherein in a cross-sectional view, an inner region of the first semiconductor layer includes a first region with a first thickness, and an edge of the first semiconductor layer includes a second region with a second thickness larger than the first thickness.

Abstract: A surveillance system includes a ring-shaped track, a first support frame, at least one first roller, at least one second roller and a lens module. The ring-shaped track has an outside flanged portion and an inside flanged portion. The at least one first roller is disposed on the first support frame and leans against the outside flanged portion. The at least one second roller is disposed on the first support frame and leans against the inside flanged portion, such that the ring-shaped track is sandwiched in between the at least one first roller and the at least one second roller. The lens module is disposed on the first support frame.

Abstract: A keyswitch structure includes a base plate, a keycap, a first support, and a second support. The keycap is located above the base plate. The first support is connected to and between the keycap and the base plate and has an upper connection portion, a lower connection portion, and a protruding limitation portion. The upper connection portion is located between the lower connection portion and the protruding limitation portion. The first support is rotatably connected to the keycap and the base plate through the upper connection portion and the lower connection portion respectively. The protruding limitation portion is located close to and under the cap body. The second support is connected to and between the keycap and the base plate. The keycap moves up and down relative to the base plate through the first support and the second support.