Patents by Inventor Chih-hao Chen

Chih-hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11239136
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die. The TIM is disposed on the first die, the second die, and the underfill layer. The adhesive pattern is disposed between the underfill layer and the TIM to separate the underfill layer from the TIM.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
  • Patent number: 11239134
    Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11222887
    Abstract: A transient voltage suppression device including a substrate of a first conductivity type, a first well of a second conductivity type, a first anode, a first cathode, and a first trigger node is provided. The first well is disposed in the substrate. The first anode is disposed in the substrate outside the first well and includes a second doped region of the second conductivity type and a third doped region of the first conductivity type disposed between the second doped region and the first doped region. The first trigger node is disposed between the first anode and the first cathode, and includes a fourth region of the first conductivity type disposed in the substrate and a fifth doped region of the second conductivity type at least partially disposed in the first well and disposed between the fourth doped region and the third doped region.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: January 11, 2022
    Assignee: IPU SEMICONDUCTOR CO., LTD.
    Inventors: Cheng-Chi Lin, Chih-Hao Chen
  • Publication number: 20210408338
    Abstract: A light-emitting device comprises a semiconductor stack emitting a light with a peak wavelength ?; and a light field adjustment layer formed on the semiconductor stack, wherein the light field adjustment layer comprises a plurality of first layers and a plurality of second layers alternately stacked on top of each other, the plurality of first layers each comprises a first optical thickness, and the plurality of second layers each comprises a second optical thickness.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 30, 2021
    Inventors: Heng-Ying CHO, Li-Yu SHEN, Chih-Hao CHEN, Keng-Lin CHUANG
  • Patent number: 11183392
    Abstract: According to an embodiment of the present disclosure, a method of manufacturing semiconductor device includes: forming a first mandrel and a second mandrel over a mask layer; depositing a spacer layer over the first mandrel and the second mandrel; forming a line-end cut pattern over the spacer layer between the first mandrel and the second mandrel; depositing a protection layer over the line-end cut pattern; etching the protection layer and exposing upper portion of the line-end cut pattern; reducing a width of the line-end cut pattern; etching the spacer layer to expose the first mandrel and the second mandrel; and patterning the mask layer using the etched spacer layer and the reduced line-end cut pattern as an etch mask.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jiann-Horng Lin, Chao-Kuei Yeh, Ying-Hao Wu, Tai-Yen Peng, Chih-Hao Chen, Chih-Sheng Tian
  • Publication number: 20210358768
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hui Cheng, Szu-Wei Lu, Ping-Yin Hsieh, Chih-Hao Chen
  • Publication number: 20210343913
    Abstract: A light-emitting device comprises a substrate comprising a sidewall, a first top surface, and a second top surface, wherein the second top surface is closer to the sidewall of the substrate than the first top surface to the sidewall of the substrate; a semiconductor stack formed on the substrate comprising a first semiconductor layer, an active layer, and a second semiconductor layer; a dicing street surrounding the semiconductor stack, and exposing the first top surface and the second top surface of the substrate; a protective layer covering the semiconductor stack; a reflective layer comprising a Distributed Bragg Reflector structure covering the protective layer; and a cap layer covering the reflective layer, wherein the second top surface of the substrate is not covered by the protective layer, the reflective layer, and the cap layer.
    Type: Application
    Filed: May 3, 2021
    Publication date: November 4, 2021
    Inventors: Hsin-Ying WANG, Chih-Hao CHEN, Chien-Chih LIAO, Chao-Hsing CHEN, Wu-Tsung LO, Tsun-Kai KO, Chen OU
  • Publication number: 20210343906
    Abstract: A light-emitting device comprises a substrate comprising a top surface and a sidewall; a semiconductor stack formed on the top surface of the substrate comprising a first semiconductor layer, an active layer and a second semiconductor layer; a dicing street surrounding the semiconductor stack and exposing the top surface of the substrate; a protective layer covering the semiconductor stack and the dicing street; a reflective layer comprising a Distributed Bragg Reflector structure and covering the protective layer; and a cap layer covering the reflective layer, wherein the reflective layer comprises an uneven portion adjacent to the sidewall of the substrate, and the uneven portion comprises an uneven thickness.
    Type: Application
    Filed: May 3, 2021
    Publication date: November 4, 2021
    Inventors: Hsin-Ying WANG, Chih-Hao CHEN, Chien-Chih LIAO, Chao-Hsing CHEN, Wu-Tsung LO, Tsun-Kai KO, Chen OU
  • Publication number: 20210343611
    Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component, and a top surface of the dam structure is higher than a top surface of the package component. The method further includes forming an underfill layer between the dam structure and the package component. In addition, the method includes removing the dam structure after the underfill layer is formed.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Inventors: Chih-Hao CHEN, Chih-Chien PAN, Li-Hui CHENG, Chin-Fu KAO, Szu-Wei LU
  • Publication number: 20210333582
    Abstract: A display panel includes a first substrate, an electrode layer, and a display medium layer. The electrode layer is disposed on the first substrate. The display medium layer is disposed on the electrode layer and includes a filler and liquid crystal capsules. The liquid crystal capsules are distributed in the filler, and the filler has a birefringence difference ?n in a range from 0.02 to 0.175.
    Type: Application
    Filed: July 6, 2021
    Publication date: October 28, 2021
    Inventors: Liang-Yin HUANG, Chih-Hao CHEN, Min-Zi HONG, Seok-Lyul LEE
  • Publication number: 20210280745
    Abstract: A method of manufacturing a light-emitting element includes: providing a substrate, wherein the substrate includes a top surface with a first area and a second area; introducing a semiconductor material to form a first layer on the first area and a second layer on the second area, wherein the first layer includes a first crystal quality and the second layer includes a second crystal quality, the first crystal quality is different from the second crystal quality; and dicing the substrate along the second area.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Inventors: Yi-Lun CHOU, Chih-Hao CHEN
  • Publication number: 20210271132
    Abstract: A display apparatus includes a backlight source, a privacy filter disposed on the backlight source, a light adjusting panel disposed on the privacy filter, and a display panel disposed on the light adjusting panel. The light adjusting panel includes a first substrate, a first electrode, a second electrode, a first vertical alignment film disposed on the first substrate, a second substrate disposed opposite to the first substrate, a second vertical alignment film disposed on the second substrate, and a positive liquid crystal layer disposed between the first vertical alignment film and the second vertical alignment film. The first electrode and the second electrode are disposed on the first substrate. Here, the first electrode has a plurality of first slits, and a plurality of orthogonal projections of the first slits on the first substrate overlap an orthogonal projection of the second electrode on the first substrate.
    Type: Application
    Filed: August 21, 2020
    Publication date: September 2, 2021
    Applicant: Au Optronics Corporation
    Inventors: Min-Hsuan Chiu, Chih-Hao Chen, Seok-Lyul Lee, Syuan-Ling Yang
  • Publication number: 20210273137
    Abstract: A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate,
    Type: Application
    Filed: May 14, 2021
    Publication date: September 2, 2021
    Inventors: Chao-Hsing CHEN, Cheng-Lin LU, Chih-Hao CHEN, Chi-Shiang HSU, I-Lun MA, Meng-Hsiang HONG, Hsin-Ying WANG, Kuo-Ching HUNG, Yi-Hung LIN
  • Patent number: 11092838
    Abstract: A display panel includes a first substrate, an electrode layer, and a display medium layer. The electrode layer is disposed on the first substrate. The display medium layer is disposed on the electrode layer and includes a filler and liquid crystal capsules. The liquid crystal capsules are distributed in the filler, and the filler has a birefringence difference ?n in a range from 0.02 to 0.175.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: August 17, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Liang-Yin Huang, Chih-Hao Chen, Min-Zi Hong, Seok-Lyul Lee
  • Patent number: 11088267
    Abstract: Provided is a semiconductor device with a diode and a silicon controlled rectifier (SCR) including a substrate having a first conductivity type, a well region having a second conductivity type, a first doped region having the first conductivity type, and a second doped region having the second conductivity type. The well region is disposed in the substrate. The first doped region is disposed in the substrate. The second doped region is disposed in the substrate. The well region and the first doped region form a first PN junction, the well region and the substrate form a second PN junction, and the substrate and the second doped region form a third junction. The first, second, and third PN junctions form the SCR, and the first doped region and the third PN junction form the diode.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: August 10, 2021
    Assignee: IPU SEMICONDUCTOR CO., LTD.
    Inventor: Chih-Hao Chen
  • Patent number: 11087853
    Abstract: A memory device includes a plurality of memory blocks and each memory block includes a plurality of columns of memory cells. Each column of memory cells is coupled to a corresponding bit line. Upon completion of a power-up sequence, detect if a current leakage of corresponding columns in a group of memory blocks is greater than a predetermined level. If the current leakage of the corresponding columns in the group of memory blocks is greater than the predetermined level, perform an over-erasure correction on the corresponding columns.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 10, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Chih-Hao Chen
  • Patent number: 11084364
    Abstract: A vehicle includes a main frame, a power unit, a power controlling unit, and a battery receiving module. The power unit, a power controlling unit, and a battery receiving module are disposed on the main frame respectively. The battery receiving module is disposed between the power unit and the power controlling unit along a front-rear direction of the vehicle.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: August 10, 2021
    Assignee: Gogoro Inc.
    Inventors: Chih-Hao Chen, Chia-Hao Chang
  • Patent number: 11081369
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hui Cheng, Szu-Wei Lu, Ping-Yin Hsieh, Chih-Hao Chen
  • Publication number: 20210225727
    Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20210226332
    Abstract: An adjustable wireless accessible point includes a base, a plurality of antenna modules and an antenna driving module. The plurality of antenna modules are movably disposed on the base and for emitting or receiving wireless signals. The antenna driving module is movably connected to the plurality of antenna modules and for driving the plurality of antenna modules to synchronously move relative to the base, so as to achieve a purpose of adjusting a radiation pattern of the adjustable wireless accessible point.
    Type: Application
    Filed: May 20, 2020
    Publication date: July 22, 2021
    Inventors: Chih-Hou Chien, Chih-Hao Chen