Patents by Inventor Chih-Hao Lin

Chih-Hao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031481
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Lin, Chia-Hao Chang, Chih-Hao Wang, Wai-Yi Lien, Chih-Chao Chou, Pei-Yu Wang
  • Publication number: 20210166972
    Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 3, 2021
    Inventors: Che-Liang CHUNG, Che-Hao Tu, KEI-WEI CHEN, Chih-Wen Liu, You-Shiang Lin, Yi-Ching Liang
  • Publication number: 20210167218
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.
    Type: Application
    Filed: February 15, 2021
    Publication date: June 3, 2021
    Inventors: Pei-Hsun Wang, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20210167193
    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Inventors: Huan-Chieh Su, Zhi-Chang Lin, Ting-Hung Hsu, Jia-Ni Yu, Wei-Hao Wu, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20210159235
    Abstract: A memory device and a method for forming the same are provided. The method includes forming a plurality of gate structures on a substrate, forming a first spacer on opposite sides of the gate structures, filling a dielectric layer between adjacent first spacers, forming a metal silicide layer on the gate structures, conformally forming a spacer material layer over the metal silicide layer, the first spacer layer and the dielectric layer, and performing an etch back process on the spacer material layer to form a second spacer on opposite sides of the metal silicide layer.
    Type: Application
    Filed: November 22, 2019
    Publication date: May 27, 2021
    Inventors: Yi-Tsung TSAI, Chia-Wei WU, Chih-Hao LIN, Chien-Chih LI
  • Publication number: 20210159196
    Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.
    Type: Application
    Filed: February 8, 2021
    Publication date: May 27, 2021
    Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
  • Patent number: 11018182
    Abstract: A pixel structure includes a light emitting diode chip and a light blocking structure. The light emitting diode chip includes a P-type semiconductor layer, an active layer, an N-type semiconductor layer, a first electrode, and K second electrodes. The active layer is located on the P-type semiconductor layer. The N-type semiconductor layer is located on the active layer. The N-type semiconductor layer has a first top surface that is distant from the active layer. The first electrode is electrically connected to the P-type semiconductor layer. The light blocking structure is located in the light emitting diode chip and defines K sub-pixel regions. The active layer and the N-type semiconductor layer are divided into K sub-portions respectively corresponding to the K sub-pixel regions by the light blocking structure. The K sub-pixel regions share the P-type semiconductor layer.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 25, 2021
    Assignee: Lextar Electronics Corporation
    Inventors: Yi-Jyun Chen, Li-Cheng Yang, Yu-Chun Lee, Shiou-Yi Kuo, Chih-Hao Lin
  • Patent number: 11011487
    Abstract: A semiconductor package is provided, including a package component and a number of conductive connectors. The package component has a number of conductive features on a surface of the package component. The conductive connectors are formed on the conductive features of the package component. The conductive features include a first conductive feature and a second conductive feature contacting a first conductive connector and a second conductive connector, respectively. The size of the first conductive feature is smaller than the size of the second conductive feature, and the height of the first conductive connector on the first conductive feature is greater than the height of the second conductive connector on the second conductive feature.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chih-Hao Lin, Chien-Kuo Chang, Tzu-Kai Lan, Chung-Chih Chen, Jr-Lin Hsu
  • Patent number: 11011462
    Abstract: The present disclosure relates to a semiconductor device. A fuse layer is arranged within a first dielectric layer. A bond pad is arranged on the first dielectric layer. A second dielectric layer is arranged along sidewall and upper surfaces of the bond pad. A passivation layer is arranged over the first and second dielectric layers, and the passivation layer having a bond pad opening overlying the bond pad and a fuse opening overlying the fuse layer. The bond pad has a bottom surface that is co-planar with a bottom surface of the passivation layer.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Chun-Yi Yang, Chih-Hao Lin, Hong-Seng Shue, Ruei-Hung Jang
  • Patent number: 11011625
    Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
  • Patent number: 11011431
    Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a sidewall substantially orthogonal to the first surface and the second surface; and a metallic layer surrounding and connected with the sidewall of the substrate, wherein the metallic layer includes an exposed surface substantially level with the first or second surface of the substrate. Further, a method of manufacturing the semiconductor structure is also disclosed.
    Type: Grant
    Filed: September 12, 2020
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Yang Yu, Chien-Kuo Chang, Chih-Hao Lin, Jung Tsung Cheng, Kuan-Lin Ho
  • Patent number: 11004959
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked wire structure and a second stacked wire structure extending above the isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first stacked wire structure and the second stacked wire structure. The semiconductor device structure also includes a capping layer formed over the dummy fin structure. The isolation structure has a first width, the dummy fin structure has a second width, and the second width is smaller than the first width.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Kuan-Ting Pan, Chih-Hao Wang, Shi-Ning Ju
  • Publication number: 20210134944
    Abstract: In some embodiments, the present disclosure relates to an integrated chip including a first transistor and a second transistor arranged over a substrate. The first transistor includes first and second source/drain regions over the substrate and includes a first channel structure directly between the first and second source/drain regions. A first gate electrode is arranged over the first channel structure and is between first and second air spacer structures. The second transistor includes third and fourth source/drain regions over the substrate and includes a second channel structure directly between the third and fourth source/drain regions. A second gate electrode is arranged over the second channel structure and is between third and fourth air spacer structures. The integrated chip further includes a high-k dielectric spacer structure over a low-k dielectric fin structure between the first and second channel structures to separate the first and second gate electrodes.
    Type: Application
    Filed: June 30, 2020
    Publication date: May 6, 2021
    Inventors: Huan-Chieh Su, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Yu-Ming Lin
  • Patent number: 10998428
    Abstract: Examples of an integrated circuit and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a substrate that includes: a plurality of fins extending above a remainder of the substrate; a first region that includes a first fence region that contains a first subset of the plurality of fins; and a second region that includes a second fence region that contains a second subset of the plurality of fins. The first region has a first performance characteristic, and the second region has a second performance characteristic that is different from the first. Based on the first performance characteristic, the first subset of the plurality of fins is recessed to a first height, and based on the second performance characteristic, the second subset of the plurality of fins is recessed to a second height that is less than the first height.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Wei-Chiang Hung, Wei-Hao Huang
  • Publication number: 20210125888
    Abstract: An electronic device is provided. The electronic device includes a substrate, an active element, a first insulation layer, and a detection element. The active element is disposed on the substrate. The first insulation layer is disposed on the active element. The detection element is disposed on the first insulation layer. The detection element comprises a lower electrode, an active layer and an upper electrode, and the lower electrode is a part of a conductive layer. The first insulation layer has a recess, and the recess does not overlap with the conductive layer in the normal direction of the substrate.
    Type: Application
    Filed: October 19, 2020
    Publication date: April 29, 2021
    Applicant: Innolux Corporation
    Inventors: Hsin-Hung Lin, Chih-Hao Wu
  • Patent number: 10991824
    Abstract: A semiconductor device includes: a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure; a second gate structure on the STI; and a third gate structure on the SDB structure, wherein a width of the third gate structure is greater than a width of the second gate structure.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: April 27, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
  • Publication number: 20210118688
    Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 22, 2021
    Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
  • Publication number: 20210064416
    Abstract: In various embodiments, a serverless function agent determines that a client stub function has been invoked with a first set of arguments in a first execution environment. The serverless function agent then performs one or more operations on a media item that is associated with a first argument included in the first set of arguments to generate a second argument included in a second set of arguments. Notably, the first argument has a first data type and the second argument has a second data type. Subsequently, the serverless function agent invokes a function with the second set of arguments in a second execution environment. Advantageously, because the serverless function agent automatically performs operations on the media item, the overall amount of technical know-how and manual effort required to enable the function to successfully execute on a wide range of media items can be reduced.
    Type: Application
    Filed: November 20, 2019
    Publication date: March 4, 2021
    Inventors: Francisco J. SAN MIGUEL, Ameya VASANI, Dmitry VASILYEV, Chih Hao LIN, Xiaomei LIU, Naveen MAREDDY, Guanhua YE, Megha MANOHARA, Anush MOORTHY
  • Publication number: 20210067841
    Abstract: In various embodiments, a function build application compiles source code to generate an executable version of a function that has a first function signature. The function build application then replaces a first data type of a first parameter included in the first function signature with a second data type to generate a second function signature for a client stub function. Subsequently, the function build application generates a remote procedure call (RPC) client that includes the client stub function. Notably, the RPC client causes the function to execute when the client stub function is invoked. Advantageously, unlike conventional techniques that require manual generation of strongly typed functions, the function build application automatically customizes the RPC client for the function.
    Type: Application
    Filed: November 20, 2019
    Publication date: March 4, 2021
    Inventors: Francisco J. SAN MIGUEL, Ameya VASANI, Dmitry VASILYEV, Chih Hao LIN, Xiaomei LIU, Naveen MAREDDY, Guanhua YE, Megha MANOHARA, Anush MOORTHY
  • Publication number: 20200411385
    Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a sidewall substantially orthogonal to the first surface and the second surface; and a metallic layer surrounding and connected with the sidewall of the substrate, wherein the metallic layer includes an exposed surface substantially level with the first or second surface of the substrate. Further, a method of manufacturing the semiconductor structure is also disclosed.
    Type: Application
    Filed: September 12, 2020
    Publication date: December 31, 2020
    Inventors: CHI-YANG YU, CHIEN-KUO CHANG, CHIH-HAO LIN, JUNG TSUNG CHENG, KUAN-LIN HO