Abstract: A memory device and a method for forming the same are provided. The method includes forming a plurality of gate structures on a substrate, forming a first spacer on opposite sides of the gate structures, filling a dielectric layer between adjacent first spacers, forming a metal silicide layer on the gate structures, conformally forming a spacer material layer over the metal silicide layer, the first spacer layer and the dielectric layer, and performing an etch back process on the spacer material layer to form a second spacer on opposite sides of the metal silicide layer.

Abstract: The light emitting diode packaging structure includes a flexible substrate, a first adhesive layer, a micro light emitting element, a conductive pad, a redistribution layer, and an electrode pad. The first adhesive layer is disposed on the flexible substrate. The micro light emitting element is disposed on the first adhesive layer. The micro light emitting element has a first surface facing to the first adhesive layer and a second surface opposite to the first surface. The conductive pad is disposed on the second surface of the micro light emitting element. The redistribution layer covers the micro light emitting element and the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer. A total thickness of the flexible substrate, the first adhesive layer, the redistribution layer, and the electrode pad is less than 200 um.

Abstract: Disclosed is a light-emitting array structure having a substrate, a plurality of light-emitting pixel units, a plurality of first signal wires, a plurality of second signal wires, and an encapsulating layer. The light-emitting pixel units are arranged in array on the substrate. Each light-emitting pixel unit includes a driving chip, a first flat layer, a first redistribution layer, a second flat layer, a second redistribution layer, and a light-emitting diode. Each first signal wire is electrically connected to a corresponding one of the first redistribution layers and extends in a first direction. The second signal wires extend in a level different from the first signal wires. Each second signal wire is electrically connected to a corresponding one of the second redistribution layers and extends in a second direction different from the first direction. The encapsulating layer covers the light-emitting pixel units, the first and second signal wires, and the substrate.

Abstract: Provided is a memory device including a plurality of stack structures disposed on a substrate; and a dielectric layer. Each stack structure includes a first conductive layer, a second conductive layer, an inter-gate dielectric layer, a metal silicide layer, and a barrier layer. The second conductive layer is disposed on the first conductive layer. The inter-gate dielectric layer is disposed between the first and second conductive layers. The metal silicide layer is disposed on the second conductive layer. The barrier layer is disposed between the metal silicide layer and the second conductive layer. The dielectric layer laterally surrounds a lower portion of the plurality of stack structures to expose a portion of the metal silicide layer of the plurality of stack structures.

Abstract: Disclosed is a light-emitting array structure having a substrate, a plurality of light-emitting pixel units, a plurality of first and second signal wires, and an encapsulating layer. The light-emitting pixel units are arranged in array on the substrate. Each light-emitting pixel unit includes a driving chip, a first flat layer, a first redistribution layer, a second flat layer, a second redistribution layer, and a light-emitting diode. Each first signal wire is electrically connected to a corresponding one of the first redistribution layers and extends in a first direction. The second signal wires extend in a level different from the first signal wires. Each second signal wire is electrically connected to a corresponding one of the second redistribution layers and extends in a second direction different from the first direction. The encapsulating layer covers the light-emitting pixel units, the first and second signal wires, and the substrate.

Abstract: A memory device and a method for forming the same are provided. The method includes forming a plurality of gate structures on a substrate, forming a first spacer on opposite sides of the gate structures, filling a dielectric layer between adjacent first spacers, forming a metal silicide layer on the gate structures, conformally forming a spacer material layer over the metal silicide layer, the first spacer layer and the dielectric layer, and performing an etch back process on the spacer material layer to form a second spacer on opposite sides of the metal silicide layer.

Abstract: The light emitting diode packaging structure includes a flexible substrate, a first adhesive layer, a micro light emitting element, a conductive pad, a redistribution layer, and an electrode pad. The first adhesive layer is disposed on the flexible substrate. The micro light emitting element is disposed on the first adhesive layer. The micro light emitting element has a first surface facing to the first adhesive layer and a second surface opposite to the first surface. The conductive pad is disposed on the second surface of the micro light emitting element. The redistribution layer covers the micro light emitting element and the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer. A total thickness of the flexible substrate, the first adhesive layer, the redistribution layer, and the electrode pad is less than 200 um.

Abstract: A light emitting diode device includes a substrate, a conductive via, first and second conductive pads, a driving chip, a flat layer, a redistribution layer, a light emitting diode, and an encapsulating layer. The substrate has a first surface and a second surface opposite thereto. The conductive via penetrates from the first surface to the second surface. The first and second conductive pads are respectively disposed on the first and second surface and in contact with the conductive via. The driving chip is disposed on the first surface. The flat layer is disposed over the first surface and covers the driving chip and the first conductive pad. The redistribution layer is disposed on the flat layer and electrically connects to the driving chip. The light emitting diode is flip-chip bonded to the redistribution layer. The encapsulating layer covers the redistribution layer and the light emitting diode.

Abstract: An optical film includes a first transparent layer and a reflective coating. The first transparent layer has a light input surface and a light output surface. A plurality of cavities are formed on the light input surface, wherein each cavity has a first linear sidewall and a second linear sidewall, the second linear sidewall is inclined to the first linear sidewall. The reflective coating is formed on the second linear sidewall of each cavity.

Abstract: A light emitting device includes an LED die and a wavelength conversion layer. The LED die has a light emitting top surface and light emitting side surfaces. The wavelength conversion layer contains quantum dots and a photosensitive material, and is located on the light emitting top surface. A light emitting module including multiple light emitting devices is also disclosed.

Abstract: The display device includes a substrate, a patterned wall, the first, second, third sub-pixels, and an optical layer. The patterned wall is disposed on the substrate and has a plurality of openings. The first sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer. The second sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer. The third sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer, wherein a first distance between a top surface of the light-emitting element and a top surface of the patterned wall is about 10 um to about 100 um. The optical layer is disposed on the patterned wall and in direct contact with at least one of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

Abstract: A method for manufacturing a dynamic random access memory includes: forming a buried bit line in a substrate; forming a plurality of buried word lines in the substrate, wherein the bottom surfaces of the buried word lines are higher than the top surface of the buried bit line; forming a bit line contact structure on the buried bit line; forming a through hole passing through the bit line contact structure, wherein the bit line contact structure is not in direct contact with the buried bit line, and the material of the bit line contact structure is different from the material of the buried bit line; forming a conductive plug between the bit line contact structure and the buried bit line; and forming a capacitor structure on the substrate.

Abstract: A light-emitting device includes a micro light-emitting diode chip (micro LED chip), a first electrical connecting layer, a second electrical connecting layer and a housing layer. The micro LED chip includes a light exit surface, a bottom surface opposite to the light exit surface and first and second electrodes located on the bottom surface. The first and second electrical connecting layers respectively connect to the first and second electrodes and extend along two opposite sidewalls to two sides of a perimeter of the light exit surface. The housing layer encloses the micro LED chip and the first and second electrical connecting layer. The light exit surface of the micro LED chip and top surfaces of the first and second electrical connecting layers are not enclosed by the housing layer.

Abstract: A semiconductor package structure includes a first package including a bonding region and a periphery region surrounding the bonding region, at least one insulating structure disposed in the bonding region of the first package, a second package disposed over the first package and the insulating structure in the bonding region, and a plurality of connectors disposed between the first package and the second package. The plurality of connectors provide electrical connection between the first package and the second package. Further, the insulating structure penetrates the first package and is spaced apart from the plurality of connectors.

Abstract: A non-volatile memory structure including a substrate, a plurality of charge storage layers, a first dielectric layer, and a control gate is provided. The charge storage layers are located on the substrate. An opening is provided between two adjacent charge storage layers. The first dielectric layer is located on the charge storage layers and on a surface of the opening. A bottom cross-sectional profile of the first dielectric layer located in the opening is a profile that is recessed on both sides. The control gate is located on the first dielectric layer and fills the opening.

Abstract: A semiconductor package is provided, including a package component and a number of conductive features. The package component has a non-planar surface. The conductive features are formed on the non-planar surface of the package component. The conductive features include a first conductive feature and a second conductive feature respectively arranged in a first position and a second position of the non-planar surface. The height of the first position is less than the height of the second position, and the size of the first conductive feature is smaller than the size of the second conductive feature.

Abstract: A dynamic random access memory and its manufacturing method are provided. The memory includes a buried bit line, a plurality of buried word lines, a bit line contact structure, and a conductive plug. The buried bit line is formed in a substrate. A bottom surface of the buried word line is higher than a top surface of the buried bit line. The bit line contact structure is formed on the buried bit line and has a through hole. The bit line contact structure is not in direct contact with the buried bit line. A material of the bit line contact structure is different from a material of the buried bit line. The conductive plug is formed between the bit line contact structure and the buried bit line and fills the through hole, so that the bit line contact structure and the buried bit line are electrically connected.

Abstract: A package includes a die on a surface of a package component. The package also includes a first die stack on the surface of the package component. The package further includes a first thermal interface material (TIM) having a first thermal conductivity and disposed on the first die stack. In addition, the package includes a second thermal interface material (TIM) having a second thermal conductivity and disposed on the die. The first thermal conductivity of the first TIM is different from the second thermal conductivity of the second TIM.

Abstract: A current sensor including a voltage generation circuit and a voltage integration circuit is provided. The voltage generation circuit is configured to generate a first voltage according to a current to be sensed. The voltage integration circuit is coupled to the voltage generation circuit and configured to receive the first voltage and a second voltage to generate an output voltage. The voltage integration circuit includes a first amplifier, a second amplifier and a first capacitor. The first amplifier is configured to receive the first voltage and the second voltage to generate a third voltage. The second amplifier is coupled to the first amplifier and configured to receive the third voltage to generate the output voltage. The first capacitor is coupled between an output terminal of the voltage generation circuit and an output terminal of the first amplifier and configured to reduce a voltage difference between the first voltage and the second voltage.

Abstract: A method for manufacturing a metal object having a solid lubricating surface layer includes: providing a metal blank having a surface; providing a plurality of microparticles and solid lubricating powder, and mixing them together, wherein the microparticles have a hardness greater than that of the surface; and projecting the microparticles and the solid lubricating powder onto the surface, wherein the microparticles cause plastic flow on the surface to form a compressive stress layer, and the solid lubricating powder adheres to the compressive stress layer to form a solid lubricating surface layer.