Patents by Inventor Chih-Hao Lin

Chih-Hao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200321297
    Abstract: A semiconductor package is provided, including a package component and a number of conductive connectors. The package component has a number of conductive features on a surface of the package component. The conductive connectors are formed on the conductive features of the package component. The conductive features include a first conductive feature and a second conductive feature contacting a first conductive connector and a second conductive connector, respectively. The size of the first conductive feature is smaller than the size of the second conductive feature, and the height of the first conductive connector on the first conductive feature is greater than the height of the second conductive connector on the second conductive feature.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Chih-Hao LIN, Chien-Kuo CHANG, Tzu-Kai LAN, Chung-Chih CHEN, Jr-Lin HSU
  • Publication number: 20200313052
    Abstract: A LED carrier includes a substrate, a conductive layer, an adhesive layer, and a reflector. The conductive layer is disposed on the substrate, and has a bonding portion and an extending portion. The bonding portion has a top surface higher than a top surface of the extending portion. The adhesive layer covers the extending portion of the conductive layer and exposes the bonding portion of the conductive layer. The reflector is disposed over the adhesive layer. The adhesive layer has a hook portion in contact with a corner of the reflector.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Inventors: Chih-Hao LIN, Chun-Peng LIN, Chang-Han CHEN, Kuang-Neng YANG, Cheng-Ta KUO
  • Patent number: 10777467
    Abstract: A semiconductor structure includes a substrate including a first surface and a second surface opposite to the first surface; a dielectric layer disposed over the second surface or below the first surface; a polymeric layer disposed over or below the dielectric layer; an isolation layer surrounding and contacted with the substrate, the dielectric layer and the polymeric layer; a die disposed over the polymeric layer; a first conductive bump disposed below the first surface of the substrate; and a second conductive bump disposed between the second surface of the substrate and the die.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Yang Yu, Chien-Kuo Chang, Chih-Hao Lin, Jung Tsung Cheng, Kuan-Lin Ho
  • Publication number: 20200286894
    Abstract: A dynamic random access memory and its manufacturing method are provided. The memory includes a buried bit line, a plurality of buried word lines, a bit line contact structure, and a conductive plug. The buried bit line is formed in a substrate. A bottom surface of the buried word line is higher than a top surface of the buried bit line. The bit line contact structure is formed on the buried bit line and has a through hole. The bit line contact structure is not in direct contact with the buried bit line. A material of the bit line contact structure is different from a material of the buried bit line. The conductive plug is formed between the bit line contact structure and the buried bit line and fills the through hole, so that the bit line contact structure and the buried bit line are electrically connected.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 10, 2020
    Inventor: Chih-Hao LIN
  • Patent number: 10741561
    Abstract: A dynamic random access memory (DRAM) structure is provided, and the DRAM structure includes a substrate, a DRAM, and a guard ring structure. The substrate includes a memory cell region. The DRAM is disposed in the memory cell region. The DRAM includes a capacitor contact coupled to a capacitor structure. The guard ring structure surrounds a border of the memory cell region. The capacitor contact and the guard ring structure originate from the same conductive layer.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 11, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Chih-Hao Lin
  • Publication number: 20200243734
    Abstract: A light-emitting device includes a panel substrate, a light-emitting chip, and a light extracting layer. The light-emitting chip is disposed on the panel substrate. The light extracting layer covers the light-emitting chip and the panel substrate, and the light extracting layer has a side portion. Taking the position where the edge of the light-emitting chip is in contact with the panel substrate as the origin, the side portion and the origin define a circle tangential to the surface of the side portion. The circle has a radius c which satisfies the following formula (1): 1/40H?c?H??(1) where H is a height of the light-emitting chip. The light-emitting device disclosed herein has a light extracting layer having a very small thickness, and provides excellent light-emitting efficiency and lifetime of the light-emitting device.
    Type: Application
    Filed: January 8, 2020
    Publication date: July 30, 2020
    Inventors: Chih-Hao LIN, Chang-Han CHEN, Chun-Peng LIN
  • Patent number: 10700030
    Abstract: A semiconductor package is provided, including a package substrate, a package component, and a number of conductive connectors. The package component has a number of conductive features on a first surface of the package component facing the package substrate. The conductive connectors electrically connect the conductive features of the package component to the package substrate. The conductive features include a first conductive feature and a second conductive feature contacting a first conductive connector and a second conductive connector, respectively. The size of the first conductive feature is smaller than the size of the second conductive feature, and the height of the first conductive connector on the first conductive feature is greater than the height of the second conductive connector on the second conductive feature.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Lin, Chien-Kuo Chang, Tzu-Kai Lan, Chung-Chih Chen, Jr-Lin Hsu
  • Publication number: 20200161275
    Abstract: A package includes a die on a surface of a package component. The package also includes a first die stack on the surface of the package component. The package further includes a first thermal interface material (TIM) having a first thermal conductivity and disposed on the first die stack. In addition, the package includes a second thermal interface material (TIM) having a second thermal conductivity and disposed on the die. The first thermal conductivity of the first TIM is different from the second thermal conductivity of the second TIM.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 21, 2020
    Inventors: Chih-Hao LIN, Chien-Kuo CHANG, Pu-Sheng LEE, Fu-Jen LI, Hsien-Liang MENG
  • Publication number: 20200066598
    Abstract: A semiconductor structure includes a substrate including a first surface and a second surface opposite to the first surface; a dielectric layer disposed over the second surface or below the first surface; a polymeric layer disposed over or below the dielectric layer; an isolation layer surrounding and contacted with the substrate, the dielectric layer and the polymeric layer; a die disposed over the polymeric layer; a first conductive bump disposed below the first surface of the substrate; and a second conductive bump disposed between the second surface of the substrate and the die.
    Type: Application
    Filed: November 4, 2019
    Publication date: February 27, 2020
    Inventors: CHI-YANG YU, CHIEN-KUO CHANG, CHIH-HAO LIN, JUNG TSUNG CHENG, KUAN-LIN HO
  • Publication number: 20200058611
    Abstract: A semiconductor package is provided, including a package substrate, a package component, and a number of conductive connectors. The package component has a number of conductive features on a first surface of the package component facing the package substrate. The conductive connectors electrically connect the conductive features of the package component to the package substrate. The conductive features include a first conductive feature and a second conductive feature contacting a first conductive connector and a second conductive connector, respectively. The size of the first conductive feature is smaller than the size of the second conductive feature, and the height of the first conductive connector on the first conductive feature is greater than the height of the second conductive connector on the second conductive feature.
    Type: Application
    Filed: January 28, 2019
    Publication date: February 20, 2020
    Inventors: Chih-Hao LIN, Chien-Kuo CHANG, Tzu-Kai LAN, Chung-Chih CHEN, Jr-Lin HSU
  • Publication number: 20200006347
    Abstract: A dynamic random access memory (DRAM) structure is provided, and the DRAM structure includes a substrate, a DRAM, and a guard ring structure. The substrate includes a memory cell region. The DRAM is disposed in the memory cell region. The DRAM includes a capacitor contact coupled to a capacitor structure. The guard ring structure surrounds a border of the memory cell region. The capacitor contact and the guard ring structure originate from the same conductive layer.
    Type: Application
    Filed: September 10, 2019
    Publication date: January 2, 2020
    Applicant: Winbond Electronics Corp.
    Inventor: Chih-Hao Lin
  • Patent number: 10468307
    Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a first sidewall substantially orthogonal to the first surface and the second surface; an isolation layer surrounding and contacted with the first sidewall of the substrate; a die disposed over the second surface of the substrate; a first conductive bump disposed at the first surface of the substrate; and a second conductive bump disposed between the substrate and the die.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Yang Yu, Chien-Kuo Chang, Chih-Hao Lin, Jung Tsung Cheng, Kuan-Lin Ho
  • Patent number: 10453848
    Abstract: A manufacturing method of a dynamic random access memory (DRAM) structure includes following steps. A substrate is provided, wherein the substrate includes a memory cell region and a peripheral circuit region. A DRAM is formed in the memory cell region and includes a capacitor contact coupled to a capacitor structure. A transistor structure with a metal gate structure is formed in the peripheral circuit region. The metal gate structure is formed by a manufacturing process using a dummy gate. The capacitor contact and the dummy gate are formed by the same conductive layer.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: October 22, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Chih-Hao Lin
  • Publication number: 20190318987
    Abstract: A semiconductor package structure includes a first package including a bonding region and a periphery region surrounding the bonding region, at least one insulating structure disposed in the bonding region of the first package, a second package disposed over the first package and the insulating structure in the bonding region, and a plurality of connectors disposed between the first package and the second package. The plurality of connectors provide electrical connection between the first package and the second package. Further, the insulating structure penetrates the first package and is spaced apart from the plurality of connectors.
    Type: Application
    Filed: April 13, 2018
    Publication date: October 17, 2019
    Inventors: CHIH-HAO LIN, CHIEN-KUO CHANG, TZU-KAI LAN, HUI-TING LIN, CHUN-MIN LIN
  • Patent number: 10386629
    Abstract: A light-enhancement device includes a wavelength conversion member and a wavelength controlling element. The wavelength conversion member includes a light-transmissive substrate and wavelength conversion material which is disposed within the light-transmissive substrate for converting a portion of light with a first wavelength into another light with a second wavelength. The wavelength controlling element is disposed on a surface of the light-transmissive substrate for reflecting another portion of the light with the first wavelength into the light-transmissive substrate and enabling the portion of the light with the second wavelength to pass through the wavelength controlling element. A roughness of the surface of the light-transmissive substrate facing towards the wavelength controlling element is configured to be 0-1 ?m.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: August 20, 2019
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Chih-Hao Lin, Hui-Ru Wu, Jo-Hsiang Chen, Tzong-Liang Tsai
  • Patent number: 10312408
    Abstract: A light emitting diode chip scale packaging structure and a direct type backlight module are disclosed. The light emitting diode chip scale packaging structure includes a light emitting diode chip, a wavelength converting layer, a diffusion structure and a lens. The wavelength converting layer is disposed on the light emitting diode chip and directly contacting the light emitting diode chip, and the wavelength converting layer includes phosphor powders. The diffusion structure covers the light emitting diode chip and the wavelength converting layer, a ratio of a height of the diffusion structure to a width of the diffusion structure is 1:2 to 5:4, and the lens covers the diffusion structure. An outer surface of the lens is a free-form surface, and a material of the lens is different from a material of the diffusion structure.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: June 4, 2019
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Che-Hsuan Huang, Hsin-Lun Su, Shu-Hsiu Chang, Chih-Hao Lin, Tzong-Liang Tsai
  • Publication number: 20190131342
    Abstract: A pixel structure includes a light emitting diode chip and a light blocking structure. The light emitting diode chip includes a P-type semiconductor layer, an active layer, an N-type semiconductor layer, a first electrode, and K second electrodes. The active layer is located on the P-type semiconductor layer. The N-type semiconductor layer is located on the active layer. The N-type semiconductor layer has a first top surface that is distant from the active layer. The first electrode is electrically connected to the P-type semiconductor layer. The light blocking structure is located in the light emitting diode chip and defines K sub-pixel regions. The active layer and the N-type semiconductor layer are divided into K sub-portions respectively corresponding to the K sub-pixel regions by the light blocking structure. The K sub-pixel regions share the P-type semiconductor layer.
    Type: Application
    Filed: October 25, 2018
    Publication date: May 2, 2019
    Inventors: Yi-Jyun CHEN, Li-Cheng YANG, Yu-Chun LEE, Shiou-Yi KUO, Chih-Hao LIN
  • Publication number: 20190088552
    Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a first sidewall substantially orthogonal to the first surface and the second surface; an isolation layer surrounding and contacted with the first sidewall of the substrate; a die disposed over the second surface of the substrate; a first conductive bump disposed at the first surface of the substrate; and a second conductive bump disposed between the substrate and the die.
    Type: Application
    Filed: September 18, 2017
    Publication date: March 21, 2019
    Inventors: CHI-YANG YU, CHIEN-KUO CHANG, CHIH-HAO LIN, JUNG TSUNG CHENG, KUAN-LIN HO
  • Publication number: 20190015241
    Abstract: An ostomy pouching device for the removal of biological waste from a patient. An embodiment of an ostomy pouching device includes an outer container housing an inner bag for receiving waste from a patient's bowel. The device includes a bowel connector to connect the bowel to the inner bag. The outer container includes an air exit aperture through which air may exit the container as it is displaced as the inner bag expands, and a gas tunnel for removing gas from the inner bag.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 17, 2019
    Inventors: Chih-Hao Lin, Wan-Chen Shen, Wei-Ting Shih
  • Patent number: 10141476
    Abstract: A light emitting diode chip scale packaging structure is disclosed. The light emitting diode chip scale packaging structure comprises a light emitting diode chip and a lens. The lens covers the light emitting diode chip. A curve of an outer surface of the lens in a cross-section view substantially complies with a polynomial of: z=?i=0nai*yi, A center point of the curve corresponding to the light emitting diode chip is a zero point of y-z coordinate axes. z is a variable of vertical axis of the curve. y is a variable of horizontal axis of the curve. ai is a constant coefficient in a term of ith degree. 3<n?6.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: November 27, 2018
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Che-Hsuan Huang, Shu-Hsiu Chang, Hsin-Lun Su, Chih-Hao Lin, Tzong-Liang Tsai