Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: A semiconductor device includes a first active region, a second active region and a dielectric wall. The second active region disposed adjacent to the first active region, and there is a first space between the first active region and the second active region. The dielectric wall is formed within the first space and has a first sidewall and a second sidewall opposite to the first sidewall. The first sidewall and the second sidewall opposite to the first sidewall continuously extend along a plane.

Abstract: A method includes forming a first waveguide over a substrate; forming a first layer of low-dimensional material on the first waveguide; forming a first layer of dielectric material over the first layer of low-dimensional material; forming a second layer of low dimensional material on the first layer of dielectric material; and forming a first conductive contact that electrically contacts the first layer of low-dimensional material and a second conductive contact that electrically contacts the second layer of low-dimensional material.

Abstract: The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a stack of semiconductor layers comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers over a semiconductor substrate. A first stack of masking layers is formed over the stack of semiconductor layers with a first width and a second stack of masking layers is formed laterally offset from the stack of semiconductor layers with a second width less than the first width. A patterning process is performed on the semiconductor substrate and the stack of semiconductor layers, thereby defining a first fin structure laterally adjacent to a second fin structure. The first fin structure has the first width and the second fin structure has the second width. The stack of semiconductor layers directly overlies the first fin structure and has the first width.

Abstract: A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

Abstract: An X ray device, including an array substrate, a scintillator layer, a first adhesion layer, a function film, and a second adhesion layer, is provided. The scintillator layer is disposed on the array substrate. The first adhesion layer is disposed between the scintillator layer and the array substrate. The function film is disposed on the array substrate. The second adhesion layer is disposed between the function film and the array substrate. The function film covers the scintillator layer.

Abstract: Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.

Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain feature on a semiconductor fin structure, a first isolation structure surrounding the semiconductor fin structure, source/drain spacers on the first isolation structure and surrounding a lower portion of the source/drain feature, a dielectric fin structure adjoining and in direct contact with the first isolation structure and one of the source/drain spacers, and an interlayer dielectric layer over the source/drain spacers and the dielectric fin structure and surrounding an upper portion of the source/drain feature.

Abstract: A semiconductor transistor device includes a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The gate structure wraps around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are disposed on opposite endings of the channel structure. The gate contact is disposed on the gate structure. The back-side source/drain contact is disposed under the first source/drain epitaxial structure. The first source/drain epitaxial structure has a concave bottom surface contacting the back-side source/drain contact.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first source/drain region disposed under a well portion, a second source/drain region disposed adjacent the first source/drain region, a dielectric material disposed between the first and second source/drain regions, and a conductive contact having a first portion disposed under the first source/drain region and a second portion disposed adjacent the first source/drain region. The second portion is disposed in the dielectric material. The structure further includes a conductive feature disposed in the dielectric material, and the conductive feature is electrically connected to the conductive contact. The conductive feature has a top surface that is substantially coplanar with a top surface of the well portion.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: A light-adjusting device having first regions and second regions is provided. The light-adjusting device includes pillars that form several groups of meta structures. The groups of meta structures correspond to the first regions, and from a top view, the first regions and the second regions are arranged in a checkerboard pattern.

Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.