Patents by Inventor Chih-Hao Wang

Chih-Hao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200203176
    Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.
    Type: Application
    Filed: January 10, 2019
    Publication date: June 25, 2020
    Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Jhao-Hao Lee, Sho-Shen Lee, Chih-Yu Chiang
  • Publication number: 20200203280
    Abstract: A semiconductor package structure and manufacturing method thereof are provided. The semiconductor package structure includes a package structure and a rigid-flexible substrate. The package structure includes semiconductor dies, a molding compound and a redistribution layer. The molding compound laterally encapsulates the semiconductor dies. The redistribution layer is disposed at a front side of the semiconductor dies and electrically connected to the semiconductor dies. The rigid-flexible substrate is disposed at a side of the redistribution layer opposite to the semiconductor dies, and includes rigid structures, a flexible core and a circuit layer. The rigid structures respectively have an interconnection structure therein. The interconnection structures are electrically connected to the redistribution layer. The flexible core laterally penetrates and connects the rigid structures.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 25, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Chung-Shi Liu, Chih-Yuan Chang, Jiun-Yi Wu, Jeng-Shien Hsieh, Tin-Hao Kuo
  • Patent number: 10692817
    Abstract: A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chuei-Tang Wang, Chen-Hua Yu, Chih-Yuan Chang
  • Patent number: 10693003
    Abstract: An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chang, Jeff J. Xu, Chien-Hsun Wang, Chih Chieh Yeh, Chih-Hsiang Chang
  • Publication number: 20200183262
    Abstract: An optical element adjusting device includes an outer frame; an inner frame framing an optical element and disposed in the outer frame; a first adjusting structure, including a first adjusting part connected to one of two opposite outer sides of the inner frame, and movably disposed through the outer frame; and a second adjusting structure, including a through channel formed in the outer frame and having connected first and second sub-channels, a second adjusting part connected to the other outer side and movably disposed in the first sub-channel, an adjusting element movably disposed in the second sub-channel, and a rolling element disposed in the through channel and between the second adjusting part and the adjusting element. The position of the optical element can be adjusted by rotating the rolling element through the adjusting element. An electronic device including the optical element adjusting device is also provided.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 11, 2020
    Inventors: CHIH-HAO WANG, CHIA-JUN CHEN
  • Patent number: 10680078
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
  • Patent number: 10679856
    Abstract: A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure and a fin isolation structure over a substrate, and forming a metal stack over the fin structure and the fin isolation structure. The method for forming a FinFET device structure also includes partially removing the metal stack so that a top surface of the fin isolation structure is exposed, and forming a dielectric material over the metal stack and covering the top surface of the fin isolation structure. The method for forming a FinFET device structure further includes patterning the dielectric material and the metal stack to form a metal gate structure and an insulating structure over the metal gate structure.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Ni Yu, Zhi-Chang Lin, Wei-Hao Wu, Huan-Chieh Su, Chung-Wei Hsu, Chih-Hao Wang
  • Publication number: 20200176590
    Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate, an insulator fin over the semiconductor substrate, the insulator fin having a principle dimension, from a cross sectional perspective, perpendicular to a top surface of the semiconductor substrate, and a semiconductor capping layer cover the insulator fin along the principle dimension. A method for manufacturing a semiconductor structure is also disclosed in the present disclosure.
    Type: Application
    Filed: June 19, 2019
    Publication date: June 4, 2020
    Inventors: CHI-YI CHUANG, CHING-WEI TSAI, KUAN-LUN CHENG, CHIH-HAO WANG
  • Publication number: 20200176449
    Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a plurality of nanostructures stacked over a substrate in a vertical direction, a source/drain terminal adjoining the plurality of nanostructures, and a gate structure around the plurality of nanostructures. The gate structure includes a metal cap connecting adjacent two of the plurality of nanostructures and a metal layer partially surrounding the plurality of nanostructures.
    Type: Application
    Filed: February 4, 2020
    Publication date: June 4, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng CHING, Shi Ning JU, Ching-Wei TSAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20200174187
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes a substrate and a dielectric layer. The substrate has a wave guide pattern. The dielectric layer is disposed over the substrate. The photonic die is encapsulated by the encapsulant. The wave guide structure spans over the front side of the photonic die and a top surface of the encapsulant, and penetrates the dielectric layer to be optically coupled with the wave guide pattern.
    Type: Application
    Filed: September 13, 2019
    Publication date: June 4, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Publication number: 20200176585
    Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.
    Type: Application
    Filed: October 8, 2019
    Publication date: June 4, 2020
    Inventors: Bo-Feng Young, Chih-Yu Chang, Sai-Hooi Yeong, Chi On Chui, Chih-Hao Wang
  • Patent number: 10672892
    Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 10672769
    Abstract: A method includes forming a transistor over a substrate, wherein the transistor includes a source, a drain over the source, a semiconductor channel between the source and the drain, and a gate surrounding the semiconductor channel. A silicide layer is formed over the drain of the transistor. A capping layer is formed over the silicide layer. Portions of the capping layer and the silicide layer are removed to define a drain pad over the drain of the transistor.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Wai-Yi Lien, Chih-Hao Wang
  • Patent number: 10672570
    Abstract: A keyswitch structure includes a base plate, a keycap, a first support, and a second support. The keycap is located above the base plate. The first support is connected to and between the keycap and the base plate and has an upper connection portion, a lower connection portion, and a protruding limitation portion. The upper connection portion is located between the lower connection portion and the protruding limitation portion. The first support is rotatably connected to the keycap and the base plate through the upper connection portion and the lower connection portion respectively. The protruding limitation portion is located close to and under the cap body. The second support is connected to and between the keycap and the base plate. The keycap moves up and down relative to the base plate through the first support and the second support.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: June 2, 2020
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Chih-Hao Chen, Po-Wei Tsai, Chun-Yuan Wang, Kuan-Te Lin, Shao-Wei Yang, Ling-Hsi Chao
  • Publication number: 20200166794
    Abstract: An electronic device having a display panel is provided. The display panel includes a first pixel circuit, a second pixel circuit, a first signal line, a second signal line and a first buffer circuit unit. The second pixel circuit is adjacent to the first pixel circuit. The first signal line is electrically connected to the first pixel circuit. The second signal line is electrically connected to the second pixel circuit. The first buffer circuit unit is disposed between the first pixel circuit and the second pixel circuit. At least a portion of the first pixel circuit and at least a portion of the second pixel circuit are disposed between the first signal line and the second signal line.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 28, 2020
    Inventors: Chang-Chiang CHENG, Huai-Ping HUANG, Yung-Hsun WU, Peng-Wen Wang, Chih-Lung LIN, Chia-Hao TSAI
  • Publication number: 20200168555
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.
    Type: Application
    Filed: October 9, 2019
    Publication date: May 28, 2020
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20200168742
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.
    Type: Application
    Filed: July 15, 2019
    Publication date: May 28, 2020
    Inventors: Pei-Hsun Wang, Chun-Hsiung Lin, Chih-Hao Wang
  • Patent number: 10665691
    Abstract: A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a lower portion and an upper portion extending upwards from the lower portion. The bottom capping structure covers a sidewall of the lower portion of the fin. The top capping structure covers a sidewall of the upper portion of the fin.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Chih-Hao Wang, Ying-Keung Leung
  • Publication number: 20200161439
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device according to the present disclosure includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a gate cut feature adjacent the gate structure, a source/drain contact isolation feature adjacent the source/drain contact, a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and an air gap sandwiched between the spacer and the liner. The gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.
    Type: Application
    Filed: May 8, 2019
    Publication date: May 21, 2020
    Inventors: Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 10658245
    Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Ting Pan