Patents by Inventor Chih-Hao Wang

Chih-Hao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916125
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: February 27, 2024
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Patent number: 11916128
    Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11913876
    Abstract: An optical water-quality detection apparatus includes a detection device, a biofilm-inhibition light source, a detection light source and a sensor. The detection device includes a detection chamber. The biofilm-inhibition light source is disposed outside the detection chamber and configured to emit biofilm-inhibition light. The detection light source is disposed outside the detection chamber and configured to emit detection light. The sensor is configured to sense the detection light penetrating the detection chamber. A beam of the detection light and a beam of the inhibition light overlaps as penetrating the detection chamber.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: February 27, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Jung Chang, Jui-Hung Tsai, Ying-Hao Wang, Chih-Hao Hsu
  • Patent number: 11916072
    Abstract: A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan You, Chia-Hao Chang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11916133
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Lin-Yu Huang, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11915972
    Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20240063093
    Abstract: A semiconductor device is provided. The semiconductor device has a stack of parallel metal gates formed on a first side of a substrate, a first pair of insulation regions extending across the stack of parallel metal gates, a second pair of insulation regions replacing two of the parallel metal gates, a first isolated region enclosed by the first and second pairs of insulation layers, a first via formed within the isolated region, and an insulation layer replacing the metal gates located within the isolated region. Tree or more metal gates are located within the isolated region, and the first via extends through a portion of a center one of the three metal gates within the isolated region.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Inventors: Yi-Bo LIAO, Chun-Yuan CHEN, Lin-Yu HUANG, Yi-Hsun CHIU, Chih-Hao WANG
  • Publication number: 20240063065
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming first, second and third fin structures over a substrate, forming a first dielectric material along a first trench between the first fin structure and the second fin structure and along a second trench between the second fin structure and the third fin structure, removing a first portion of the first dielectric material along the second trench while leaving a second portion of the first dielectric material along the first trench as a dielectric liner, depositing a second dielectric material over the dielectric liner and filling the first trench and the second trench, and etching back the second dielectric material until the dielectric liner is exposed. A first portion of the second dielectric material remaining in the first trench forms a dielectric wall.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Rong LIN, Kuo-Cheng CHIANG, Shi-Ning JU, Guan-Lin CHEN, Chih-Hao WANG
  • Publication number: 20240063125
    Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Chih-Chao Chou, Wen-Ting Lan, Chih-Hao Wang
  • Publication number: 20240064952
    Abstract: A semiconductor memory device includes a first dielectric wall, a second dielectric wall, first channel portions, second channel portions, an isolation wall, and a dielectric feature. The second dielectric wall is spaced apart from the first dielectric wall in a first direction. The first channel portions are disposed on a side of the first dielectric wall and are spaced apart from each other in a second direction transverse to the first direction. The second channel portions are disposed on a side of the second dielectric wall and are spaced apart from each other in the second direction. The isolation wall is located between the first dielectric wall and the second dielectric wall. The dielectric feature is disposed to separate the first dielectric wall and the isolation wall, and is disposed on the other side of the first dielectric wall opposite to the first channel portions in the first direction.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Rong LIN, Kuo-Cheng CHIANG, Shi-Ning JU, Guan-Lin CHEN, Chih-Hao WANG
  • Patent number: 11908744
    Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes an isolation layer formed around the first fin structure and covering a sidewall of the first fin structure and a gate stack formed over the first fin structure and the isolation layer. The semiconductor device structure further includes a first source/drain structure formed over the first fin structure and spaced apart from the gate stack and a contact structure formed over the first source/drain structure. The semiconductor device structure includes a dielectric structure formed through the contact structure. In addition, the contact structure and the dielectric structure has a first slope interface that slopes downwardly from a top surface of the contact structure to a top surface of the isolation layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240055479
    Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a fin structure protruding from a substrate, wherein the fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked. The method includes forming a dummy gate structure across the fin structure. The method includes forming a gate spacer on the sidewall of the dummy gate structure. The method includes removing the dummy gate structure to expose the fin structure. The method includes partially removing the second semiconductor material layers to form concave portions on sidewalls of the second semiconductor material layers. The method includes forming dielectric spacers in the concave portions. The method includes removing the first semiconductor material layers to form gaps. The method includes forming a gate structure in the gaps to wrap around the second semiconductor material layers and the dielectric spacers.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shi-Ning JU, Yi-Ruei JHAN, Wei-Ting WANG, Chih-Hao WANG
  • Publication number: 20240055478
    Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a first fin structure and a second fin structure over a substrate. The method also includes forming a first metal gate stack wrapped around and extending across the first fin structure and the second fin structure. The method further includes forming a second metal gate stack wrapped around and extending across the first fin structure and the second fin structure. In addition, the method includes forming a protective structure extending into the first gate stack and forming a dielectric structure extending into the protective structure and the second metal gate stack. A portion of the protective structure is between the dielectric structure and the metal gate stack.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Chien CHENG, Kuo-Cheng CHIANG, Shi-Ning JU, Guan-Lin CHEN, Chih-Hao WANG
  • Publication number: 20240055502
    Abstract: A method of forming a semiconductor device includes etching trenches in a substrate to form semiconductor fins, filling a first one of the trenches with a dielectric fin, forming an insulation material in a second one of the trenches, performing a first recessing process to recess the insulation material and form a gap on a top of the dielectric fin, filling the gap with a dielectric cap, and forming a gate stack across the semiconductor fins and the dielectric fin.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 15, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guan-Lin CHEN, Kuo-Cheng CHIANG, Shi Ning JU, Jung-Chien CHENG, Chih-Hao WANG
  • Patent number: 11901364
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Hung Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11901428
    Abstract: A semiconductor device includes nanostructures vertically arranged and spaced apart from one another along a first direction. The semiconductor device also includes a dielectric fin structure of a dielectric material of uniform composition and an isolation structure on opposite sides of the nanostructures. Moreover, the semiconductor device also includes a gate structure wrapping around the nanostructures. The gate structure extends between the nanostructure and the dielectric fin structure, and extends between the nanostructures and the isolation structure. Furthermore, the nanostructures are spaced apart from the dielectric fin structure along a second direction perpendicular to the first direction by a first distance, and from the isolation structure along the second direction by a second distance, where the first distance is greater than the second distance. Additionally, the gate structure interfaces with the dielectric fin structure on a surface extending perpendicular to the first direction.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Lo-Heng Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11901456
    Abstract: A semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The first semiconductor fin connects the source feature and the drain feature. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 11901365
    Abstract: A finFET device that includes a substrate and at least one semiconductor fin extending from the substrate. The fin may include a plurality of wide portions comprising a first semiconductor material and one or more narrow portions. The one or more narrow portions have a second width less than the first width of the wide portions. Each of the one or more narrow portions separates two of the plurality of wide portions from one another such that the plurality of wide portions and the one or more narrow portions are arranged alternatingly in a substantially vertical direction that is substantially perpendicular with a surface of the substrate. The fin may also include a channel layer covering sidewalls of the plurality of wide portions and a sidewall of the one or more narrow portions.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wang-Chun Huang, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11901238
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor, a conductive feature on the transistor, a dielectric layer over the conductive feature, and an electrical connection structure in the dielectric layer and on the conductive feature. The electrical connection structure includes a first grain of a first metal material and a first inhibition layer extending along a grain boundary of the first grain of the first metal material, the first inhibition layer is made of a second metal material, and the first metal material and the second metal material have different oxidation/reduction potentials.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chuan Chiu, Jia-Chuan You, Chia-Hao Chang, Chun-Yuan Chen, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11901424
    Abstract: A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang