Patents by Inventor Chih-Hao Wang

Chih-Hao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12347748
    Abstract: A semiconductor device is provided. The semiconductor device has a stack of parallel metal gates formed on a first side of a substrate, a first pair of insulation regions extending across the stack of parallel metal gates, a second pair of insulation regions replacing two of the parallel metal gates, a first isolated region enclosed by the first and second pairs of insulation layers, a first via formed within the isolated region, and an insulation layer replacing the metal gates located within the isolated region. Tree or more metal gates are located within the isolated region, and the first via extends through a portion of a center one of the three metal gates within the isolated region.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: July 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Bo Liao, Chun-Yuan Chen, Lin-Yu Huang, Yi-Hsun Chiu, Chih-Hao Wang
  • Patent number: 12349456
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: July 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Shi-Ning Ju, Yi-Ruei Jhan, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12349378
    Abstract: The present disclosure provides a method for using a hard mask layer on a top surface of fin structures to form a fin-top mask layer. The fin-top mask layer can function as an etch stop for subsequent processes. Using the fin-top hard mask layer allows a thinner conformal dielectric layer to be used to protect semiconductor fins during the subsequent process, such as during etching of sacrificial gate electrode layer. Using a thinner conformal dielectric layer can reduce the pitch of fins, particularly for input/output devices.
    Type: Grant
    Filed: July 23, 2022
    Date of Patent: July 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Ruei Jhan, Kuan-Ting Pan, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12349407
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure also includes a gate structure including a first portion wrapping around the first nanostructures and a second portion wrapping around the second nanostructures. The semiconductor structure also includes a dielectric feature sandwiched between the first portion and the second portion of the gate structure. In addition, the dielectric feature includes a bottom portion and a top portion over the bottom portion, and the top portion of the dielectric feature includes a shell layer and a core portion surrounded by the shell layer.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: July 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Yi-Ruei Jhan, Shi-Ning Ju, Chih-Hao Wang
  • Patent number: 12349409
    Abstract: A device includes a substrate. A channel region of a transistor overlies the substrate and a source/drain region is in contact with the channel region. The source/drain region is adjacent to the channel region along a first direction. A source/drain contact is disposed on the source/drain region. A gate electrode is disposed on the channel region and a gate contact is disposed on the gate electrode. A first low-k dielectric layer is disposed between the gate contact and the source/drain contact along the first direction.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: July 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Huan Jao, Huan-Chieh Su, Yi-Bo Liao, Cheng-Chi Chuang, Jin Cai, Chih-Hao Wang
  • Patent number: 12347775
    Abstract: Corner portions of a semiconductor fin are kept on the device while removing a semiconductor fin prior to forming a backside contact. The corner portions of the semiconductor fin protect source/drain regions from etchant during backside processing. The corner portions allow the source/drain features to be formed with a convex profile on the backside. The convex profile increases volume of the source/drain features, thus, improving device performance. The convex profile also increases processing window of backside contact recess formation.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: July 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lo-Heng Chang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Shih-Cheng Chen, Shi-Ning Ju, Chih-Hao Wang
  • Publication number: 20250212505
    Abstract: A semiconductor structure includes first and second channel structures, an isolation structure, a gate structure, first and second epitaxial features, and a dielectric layer. The isolation structure is disposed between the first and second channel structures. A top surface of the isolation structure comprises a first portion adjacent the first channel structure and a second portion equidistant from the first channel structure and the second channel structure, wherein the first portion is higher than the second portion. The gate structure is disposed over the first and second channel structures. The first epitaxial feature is adjacent to a sidewall of the first channel structure. The second epitaxial feature is adjacent to a sidewall of the second channel structure. The dielectric layer is between the first channel structure and the second channel structure. The dielectric layer is over the second portion of the isolation structure and has a U-shaped cross-sectional profile.
    Type: Application
    Filed: March 11, 2025
    Publication date: June 26, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng CHING, Shi-Ning JU, Chih-Hao WANG
  • Patent number: 12342587
    Abstract: An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang Lin, Chien Ning Yao, Shih-Cheng Chen, Jung-Hung Chang, Tsung-Han Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 12342616
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.
    Type: Grant
    Filed: March 22, 2024
    Date of Patent: June 24, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chih-Hao Wang, Chien Ning Yao, Kuo-Cheng Chiang
  • Patent number: 12342604
    Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Chih-Hao Wang, Kuan-Lun Cheng, Yen-Ming Chen
  • Publication number: 20250203955
    Abstract: A device and method of forming a device are provided. The method includes forming a stack of nanostructure channels over a substrate by forming a source/drain opening. The method also includes forming a sacrificial source/drain in the source/drain opening. The method further includes increasing tensile strain of the stack of nanostructure channels by replacing the sacrificial source/drain with a replacement source/drain having germanium concentration that exceeds that of the sacrificial source/drain.
    Type: Application
    Filed: June 4, 2024
    Publication date: June 19, 2025
    Inventors: Hsien-Chih HUANG, Guan-Lin CHEN, Chia-Hao YU, Pei-Yu WANG, Chih-Hao WANG
  • Publication number: 20250201581
    Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.
    Type: Application
    Filed: February 28, 2025
    Publication date: June 19, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung-Kun CHU, Jia-Ni YU, Chun-Fu LU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250203931
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a stack of semiconductor nanostructures and a first epitaxial structure and a second epitaxial structure sandwiching one or more of the stack of semiconductor nanostructures. The semiconductor device structure also includes a backside conductive contact electrically connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the stack of semiconductor nanostructures. The semiconductor device structure further includes an insulating spacer beside a second portion of the backside conductive contact extending towards the second epitaxial structure.
    Type: Application
    Filed: March 4, 2025
    Publication date: June 19, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Chieh SU, Chun-Yuan CHEN, Li-Zhen YU, Shih-Chuan CHIU, Cheng-Chi CHUANG, Chih-Hao WANG
  • Publication number: 20250203970
    Abstract: A method for fabricating a semiconductor device is disclosed. The method involves forming a stack of alternating semiconductor channels and interposers on a substrate, with sacrificial structures between the interposers. Source/drain openings are formed, and strain in the channels is modified. Source/drain structures are formed in the openings, and dielectric layers are deposited. The resulting device features stacked nanostructures with inner spacers of varying heights, enabling improved performance in electronic devices.
    Type: Application
    Filed: May 30, 2024
    Publication date: June 19, 2025
    Inventors: Guan-Lin CHEN, Chih-Hao WANG, Chia-Hao YU, Pei-Yu WANG, Hsien-Chih HUANG
  • Publication number: 20250204020
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.
    Type: Application
    Filed: March 3, 2025
    Publication date: June 19, 2025
    Inventors: Cheng-Chi Chuang, Li-Zhen Yu, Yi-Hsun Chiu, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20250203990
    Abstract: A semiconductor device includes a substrate, a first active structure, a conductive portion and a first helmet. The first active structure is formed on the substrate and includes a plurality of first active channel sheets and a plurality of first metal gate structures vertically stacked to each other, wherein the topmost first metal gate structure includes a first inner spacer. The conductive portion is connected with the topmost first active channel sheet. The first helmet is formed above the first inner spacer and covers a lateral surface of the conductive portion.
    Type: Application
    Filed: December 13, 2023
    Publication date: June 19, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Huan JAO, Chen Luo CHENG, Sheng-Tsung WANG, Chia-Hao CHANG, Huan-Chieh SU, Chih-Hao WANG
  • Patent number: 12336226
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure also includes a first bottom layer formed adjacent to the first nanostructures, and a first dielectric liner layer formed over the first bottom layer and adjacent to the first nanostructures. The semiconductor device structure further includes a first source/drain (S/D) structure formed over the first dielectric liner layer, and the first S/D structure is isolated from the first bottom layer by the first dielectric liner layer.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hung Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien-Ning Yao, Tsung-Han Chuang, Kai-Lin Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 12336215
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The semiconductor device structure includes a first source/drain (S/D) structure formed adjacent to the gate structure, and a first S/D contact structure formed over the first S/D structure. The semiconductor device structure includes a first filling layer formed over the first S/D structure, and the first S/D contact structure is surrounded by the first filling layer. The semiconductor device structure includes a dielectric layer formed adjacent to the gate structure and the first filling layer, and the dielectric layer and the first filling layer are made of different materials. The first filling layer is surrounded by the dielectric layer.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Li-Zhen Yu, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 12336261
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: June 17, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Patent number: 12336240
    Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by dielectric barriers. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang