Patents by Inventor Chih-Hsuan Lin
Chih-Hsuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240085614Abstract: An anti-peep light source module includes a light source module and a viewing angle switching module. The light source module has a light source and a light guide plate (LGP) and has light emitting elements arranged along a first direction. The viewing angle switching module is located on a transmission path of an illumination beam of the light source module and includes a viewing angle limiting element and a viewing angle adjusting element configured to change a viewing angle of the illumination beam. The viewing angle limiting element has a grating structure and is located between the viewing angle adjusting element and the light source module. an included angle between an extension direction of the grating structure and the first direction is within a range from 88 degrees to 92 degrees. The anti-peep light source module and A display device achieve favorable optical performance, user experience, and production yield.Type: ApplicationFiled: September 8, 2023Publication date: March 14, 2024Applicant: Coretronic CorporationInventors: Yi-Cheng Lin, Chih-Hsuan Kuo, Sung-Chun Hsu, Ming-Hsiung Fan, Tzeng-Ke Shiau
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Publication number: 20240087953Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
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Publication number: 20240088307Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Patent number: 11929318Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.Type: GrantFiled: May 10, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Publication number: 20240077762Abstract: A display is disclosed. The display comprises a display panel, and an optical film disposed on a viewing side of the display panel. The optical film has a total haze ranging from 15% to 60%, an inner haze less than or equal to 10%, and a reflectivity satisfying the relationships of 0.35%?(RSCI-RSCE)?1.50% and RSCE?1.50%, wherein RSCI is an average reflectivity of diffuse component and specular component, and RSCE is an average reflectivity of diffuse component. By adjusting the total haze, inner haze and reflectivity of the optical film to satisfy the above relationship, the display can have good anti-glare properties, and the contrast ratio of the display will not be reduced too much to avoid the display quality be affected.Type: ApplicationFiled: April 10, 2023Publication date: March 7, 2024Applicant: BenQ Materials CorporationInventors: Yu-Wei Tu, Chih-Wei Lin, Kuo-Hsuan Yu
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Publication number: 20240079972Abstract: The present invention relates to a shear deformation-type bimorphic piezoelectric actuator. The actuator includes at least a pair of shear deformation-type piezoelectric ceramic members which are polarized in the height direction thereof, coated with metal electrodes on both sides thereof and attached to opposite sides of a metal block to constitute a piezoelectric bimorph. The ceramic members are forced to undergo a face shear deformation or a resonance deformation upon receiving a driving voltage, whereby the metal block and the output head mounted thereon are driven to generate an elliptical motion, which in turn drives a rotor or a carriage to move. Taking advantage of the small dimension of the ceramic members and the enhanced displacement attributed to the piezoelectric bimorph structure, the piezoelectric actuator disclosed herein is suitable for manufacturing a miniature piezoelectric motor with high power output.Type: ApplicationFiled: April 27, 2023Publication date: March 7, 2024Inventors: Yung TING, Sheuan-Perng LIN, Suhail ABBAS, Chih-Hsuan YU
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Publication number: 20240071981Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.Type: ApplicationFiled: November 1, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
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Patent number: 11894674Abstract: A power detection circuit is provided. The protection circuit is coupled to a pad and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor of a first conductivity type and a second transistor, also of the first conductivity type, which are coupled in series between the pad and a ground terminal. The trigger circuit detects whether a transient even occurs on the pad. The discharge circuit is coupled between the bonding pad and the ground terminal and controlled by the trigger circuit. In response to the transient event occurring on the bonding pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the pad and the ground terminal.Type: GrantFiled: May 11, 2022Date of Patent: February 6, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Jian-Hsing Lee, Yeh-Ning Jou, Chih-Hsuan Lin, Chang-Min Lin, Hwa-Chyi Chiou
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Patent number: 11894430Abstract: A semiconductor structure, including a substrate, a first well, a second well, a first doped region, a second doped region, a first gate structure, a first insulating layer, and a first field plate structure. The first and second wells are disposed in the substrate. The first doped region is disposed in the first well. The second doped region is disposed in the second well. The first gate structure is disposed between the first and second doped regions. The first insulating layer covers a portion of the first well and a portion of the first gate structure. The first field plate structure is disposed on the first insulating layer, and it partially overlaps the first gate structure. Wherein the first field plate structure is segmented into a first partial field plate and a second partial field plate separated from each other along a first direction.Type: GrantFiled: September 16, 2021Date of Patent: February 6, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Shao-Chang Huang, Kai-Chieh Hsu, Chun-Chih Chen, Chih-Hsuan Lin
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Publication number: 20240028813Abstract: A semiconductor layout including a semiconductor layer and a dummy layer is provided. The semiconductor layer includes a layout pattern. The dummy layer includes a dummy pattern. A check circuit calculates the layout pattern and the dummy pattern to generate a calculated value. The check circuit compares the calculated value to the predetermined value to determine whether the layout pattern has been modified.Type: ApplicationFiled: July 25, 2022Publication date: January 25, 2024Applicant: Vanguard International Semiconductor CorporationInventors: Yeh-Ning JOU, Chih-Hsuan LIN, Shu-Pin HSU, Hwa-Chyi CHIOU, Chang-Min LIN, Tsong-Shyan CHEN
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Patent number: 11871539Abstract: An electronic apparatus with a cooling system includes a chassis having a mounting slot, and a removable device. The removable device includes a housing detachably disposed in the mounting slot; a first pump disposed in the housing, and detachably affixed to a bottom of the housing; a second pump detachably affixed to the bottom of the housing, and connected to the first pump; and a tank disposed on the first pump and configured to store cooling liquid. when the first pump or the second pump is operating, the cooling liquid in the tank flows into the first pump, and the cooling liquid in the first pump flows into the second pump.Type: GrantFiled: September 13, 2022Date of Patent: January 9, 2024Assignee: Nanning FuLian FuGui Precision Industrial Co., Ltd.Inventor: Chih-Hsuan Lin
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Patent number: 11837603Abstract: A method includes forming a source/drain region for a transistor, forming a first inter-layer dielectric over the source/drain region, and forming a lower source/drain contact plug over and electrically coupling to the source/drain region. The lower source/drain contact plug extends into the first inter-layer dielectric. The method further includes depositing an etch stop layer over the first inter-layer dielectric and the lower source/drain contact plug, depositing a second inter-layer dielectric over the etch stop layer, and performing an etching process to etch the second inter-layer dielectric, the etch stop layer, and an upper portion of the first inter-layer dielectric to form an opening, with a top surface and a sidewall of the lower source/drain contact plug being exposed to the opening, and forming an upper source/drain contact plug in the opening.Type: GrantFiled: May 27, 2021Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ying-Yu Lai, Chih-Hsuan Lin, Hsi Chung Chen, Chih-Teng Liao
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Publication number: 20230387255Abstract: A semiconductor structure includes a substrate, a conductive region, a first insulation layer, a second insulation layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact. The low-k spacer is formed between a sidewall of the gate structure and the first insulation layer. The gate contact is landed on a top surface of the gate structure. A proximity distance between a sidewall of the gate contact and the conductive region contact along a top surface of the second insulation layer is in a range of from about 4 nm to about 7 nm. A method for manufacturing a semiconductor structure is also provided.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Chih-Hsuan Lin, Hsi Chung Chen, Chih-Teng Liao
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Publication number: 20230378182Abstract: A method includes forming a source/drain region for a transistor, forming a first inter-layer dielectric over the source/drain region, and forming a lower source/drain contact plug over and electrically coupling to the source/drain region. The lower source/drain contact plug extends into the first inter-layer dielectric. The method further includes depositing an etch stop layer over the first inter-layer dielectric and the lower source/drain contact plug, depositing a second inter-layer dielectric over the etch stop layer, and performing an etching process to etch the second inter-layer dielectric, the etch stop layer, and an upper portion of the first inter-layer dielectric to form an opening, with a top surface and a sidewall of the lower source/drain contact plug being exposed to the opening, and forming an upper source/drain contact plug in the opening.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Inventors: Ying-Yu Lai, Chih-Hsuan Lin, Hsi Chung Chen, Chih-Teng Liao
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Publication number: 20230369848Abstract: A power detection circuit is provided. The protection circuit is coupled to a pad and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor of a first conductivity type and a second transistor, also of the first conductivity type, which are coupled in series between the pad and a ground terminal. The trigger circuit detects whether a transient even occurs on the pad. The discharge circuit is coupled between the bonding pad and the ground terminal and controlled by the trigger circuit. In response to the transient event occurring on the bonding pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the pad and the ground terminal.Type: ApplicationFiled: May 11, 2022Publication date: November 16, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Jian-Hsing LEE, Yeh-Ning JOU, Chih-Hsuan LIN, Chang-Min LIN, Hwa-Chyi CHIOU
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Patent number: 11811222Abstract: An electrostatic discharge (ESD) protection circuit including a detection circuit, a voltage-divider element, and a discharge element is provided. The detection circuit is coupled between a first power line and a second power line. In response to an ESD event, the detection circuit enables a turn-on signal. The voltage-divider element is coupled between the first power line and a third power line and receives the turn-on signal. The discharge element is coupled between the second and third power lines. In response to the turn-on signal being enabled, the first discharge element discharges an ESD current.Type: GrantFiled: December 16, 2021Date of Patent: November 7, 2023Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Yeh-Ning Jou, Chieh-Yao Chuang, Hsien-Feng Liao, Ting-Yu Chang, Chih-Hsuan Lin, Chang-Min Lin, Shao-Chang Huang, Ching-Ho Li
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Patent number: 11810872Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.Type: GrantFiled: August 29, 2022Date of Patent: November 7, 2023Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Jian-Hsing Lee, Shao-Chang Huang, Chih-Hsuan Lin, Yu-Kai Wang, Karuna Nidhi, Hwa-Chyi Chiou
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Publication number: 20230343780Abstract: An electrostatic discharge (ESD) protection structure including a P-type substrate, a P-type structure, an N-type buried layer, an element active region, a P-type guard ring, and an N-type structure is provided. The P-type structure is formed in the P-type substrate and serves as an electrical contact of the P-type substrate. The N-type buried layer is formed in the P-type substrate. The element active region is formed on the N-type buried layer. The P-type guard ring is formed on the N-type buried layer and surrounds the element active region. The N-type structure is formed on the N-type buried layer and disposed between the P-type guard ring and the P-type structure.Type: ApplicationFiled: April 20, 2022Publication date: October 26, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Chang-Min LIN, Chih-Hsuan LIN, Yeh-Ning JOU, Hwa-Chyi CHIOU, Jian-Hsing LEE
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Publication number: 20230343637Abstract: Multiple dry etching operations are performed to form an opening for an interconnect structure, with a wet cleaning operation performed in between the dry etching operations. This multi-step etch approach increases the effectiveness of residual material removal, which increases the quality of the interconnect structure and reduces the likelihood of under etching, both of which increase semiconductor device yield and semiconductor device performance.Type: ApplicationFiled: April 25, 2022Publication date: October 26, 2023Inventors: Ying-Yu LAI, Chih-Yun WANG, Chih-Hsuan LIN, Hsi Chung CHEN
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Patent number: 11798846Abstract: The present disclosure provides embodiments of a semiconductor device. In one embodiment, the semiconductor device includes a gate structure, a source/drain feature adjacent the gate structure, a first dielectric layer over the source/drain feature, an etch stop layer over the gate structure and the first dielectric layer, a second dielectric layer over the etch stop layer, a source/drain contact that includes a first portion extending through the first dielectric layer and a second portion extending through the etch stop layer and the second dielectric layer, a metal silicide layer disposed between the second portion and etch stop layer, and a metal nitride layer disposed between the first portion and the first dielectric layer.Type: GrantFiled: January 6, 2021Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hsuan Lin, Xi-Zong Chen, Chih-Teng Liao