Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a recess in a layer. The recess has two opposite first inner walls and two opposite second inner walls, the first inner walls are spaced apart by a first distance, the second inner walls are spaced apart by a second distance, and the first distance is less than the second distance. The method includes depositing a first covering layer in the recess. The first covering layer covering the first inner walls is thinner than the first covering layer covering the second inner walls. The method includes removing the first covering layer over the first inner walls and a bottom surface of the recess.

Abstract: A driving circuit including a detection circuit, a first control circuit, a second control circuit, and a driving transistor is provided. The detection circuit is coupled between a first power terminal and a second power terminal and generates a detection signal according to the voltages of the first and second power terminals. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input-output pad and the second power terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving transistor is configured to operate according to the second control signal. The first level is different from the second level.

Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a recess in a layer. The recess has two opposite first inner walls and two opposite second inner walls, the first inner walls are spaced apart by a first distance, the second inner walls are spaced apart by a second distance, and the first distance is less than the second distance. The method includes depositing a first covering layer in the recess. The first covering layer covering the first inner walls is thinner than the first covering layer covering the second inner walls. The method includes removing the first covering layer over the first inner walls and a bottom surface of the recess.

Abstract: A semiconductor structure includes a first P-well, a first P-type diffusion region, a first N-type diffusion region, a second P-type diffusion region, and a first poly-silicon layer. The first P-type diffusion region is deposited in the first P-well and coupled to a first electrode. The first N-well is adjacent to the P-well. The first N-type diffusion region is deposited in the first N-well. The second P-type diffusion region is deposited between the first P-type diffusion region and the first N-type diffusion region, which is deposited in the first N-well. The second P-type diffusion region and the first N-type diffusion region are coupled to a second electrode. The first poly-silicon layer is deposited on the first P-type diffusion region.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a metal layer, a gate, a drain, a source and a first doping region. The substrate has a first doping type. The metal layer is adjacent to the surface of the substrate. The gate is formed on the substrate. The drain is formed in the substrate and located at one side of the gate. The drain is adjacent to the metal layer. The source is formed in the substrate and located at another side of the gate. The first doping region is formed in the substrate and surrounds the metal layer and the drain. The first doping region has a second doping type. The second doping type is different from the first doping type.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a second layer. The method includes forming a first recess and a second recess in the first layer. The first recess is narrower than the second recess. The method includes forming a first covering layer in the first recess and the second recess. The first covering layer in the first recess is thinner than the first covering layer in the second recess. The method includes removing the first covering layer in the first recess and the first covering layer covering the first bottom surface to form a first opening in the first covering layer in the second recess. The method includes removing the first portion and the second portion through the first recess and the first opening.

Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.

Abstract: The present disclosure describes a method for improving post-photolithography critical dimension (CD) uniformity for features printed on a photoresist. A layer can be formed on one or more printed features and subsequently etched to improve overall CD uniformity across the features. For example the method includes a material layer disposed over a substrate and a photoresist over the material layer. The photoresist is patterned to form a first feature with a first critical dimension (CD) and a second feature with a second CD that is larger than the first CD. Further, a layer is formed with one or more deposition/etch cycles in the second feature to form a modified second CD that is nominally equal to the first CD.

Abstract: A driving circuit including a detection circuit, a first control circuit, a second control circuit, and a driving transistor is provided. The detection circuit is coupled between a first power terminal and a second power terminal and generates a detection signal according to the voltages of the first and second power terminals. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input-output pad and the second power terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving transistor is configured to operate according to the second control signal. The first level is different from the second level.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a metal layer, a gate, a drain, a source and a first doping region. The substrate has a first doping type. The metal layer is adjacent to the surface of the substrate. The gate is formed on the substrate. The drain is formed in the substrate and located at one side of the gate. The drain is adjacent to the metal layer. The source is formed in the substrate and located at another side of the gate. The first doping region is formed in the substrate and surrounds the metal layer and the drain. The first doping region has a second doping type. The second doping type is different from the first doping type.

Abstract: A hold and release device of reduced size allowing the sliding of a server chassis relative to a rack includes a mounting assembly mounted to the server chassis. A fixing member is rotatably coupled to the mounting assembly and comprises a first protrusion to fasten the server chassis to the rack. A latching button is configured to latch the fixing member to the mounting assembly. A guiding member is connected to a button stage receives the latching button and has a sliding tunnel, and a handle slidably coupled to the guiding member is located in the sliding tunnel.

Abstract: The present disclosure describes a method for improving post-photolithography critical dimension (CD) uniformity for features printed on a photoresist. A layer can be formed on one or more printed features and subsequently etched to improve overall CD uniformity across the features. For example the method includes a material layer disposed over a substrate and a photoresist over the material layer. The photoresist is patterned to form a first feature with a first critical dimension (CD) and a second feature with a second CD that is larger than the first CD. Further, a layer is formed with one or more deposition/etch cycles in the second feature to form a modified second CD that is nominally equal to the first CD.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a second layer. The method includes forming a first recess and a second recess in the first layer. The first recess is narrower than the second recess. The method includes forming a first covering layer in the first recess and the second recess. The first covering layer in the first recess is thinner than the first covering layer in the second recess. The method includes removing the first covering layer in the first recess and the first covering layer covering the first bottom surface to form a first opening in the first covering layer in the second recess. The method includes removing the first portion and the second portion through the first recess and the first opening.

Abstract: The present disclosure describes a method for improving post-photolithography critical dimension (CD) uniformity for features printed on a photoresist. A layer can be formed on one or more printed features and subsequently etched to improve overall CD uniformity across the features. For example the method includes a material layer disposed over a substrate and a photoresist over the material layer. The photoresist is patterned to form a first feature with a first critical dimension (CD) and a second feature with a second CD that is larger than the first CD. Further, a layer is formed with one or more deposition/etch cycles in the second feature to form a modified second CD that is nominally equal to the first CD.

Abstract: A supercontinuum generation system comprises a noise-like pulse fiber laser structure, an amplification unit and a broadening medium. The noise-like pulse fiber laser structure generates at lease one noise-like pulse of the wavelength less than 1300 nm. The amplification unit includes a gain fiber with which the noise-like pulse is coupled. The broadening medium is coupled with the gain fiber. A supercontinuum is generated when the noise-like pulse is amplified by the amplification unit and broadened in spectrum by the broadening medium.

Abstract: A supercontinuum generation system comprises a noise-like pulse fiber laser structure, an amplification unit and a broadening medium. The noise-like pulse fiber laser structure generates at lease one noise-like pulse of the wavelength less than 1300 nm. The amplification unit includes a gain fiber with which the noise-like pulse is coupled. The broadening medium is coupled with the gain fiber. A supercontinuum is generated when the noise-like pulse is amplified by the amplification unit and broadened in spectrum by the broadening medium.

Abstract: A fiber laser having a ring resonance path comprises a pump light source, a Yb-doped optical fiber and a light modulation unit. The pump light source emits a pump light. The Yb-doped optical fiber is coupled with the pump light. The light modulation unit includes a grating pair, a diaphragm and two reflective elements. The grating pair is coupled with the pump light. The diaphragm includes an aperture. The light transmitted by the grating pair partially passes through the aperture and reaches one of the reflective elements to become a reflective light, and the reflective light passes through the aperture and is transmitted through the grating pair and the other reflective element to be coupled back with the ring resonance path.

Abstract: A fiber laser having a ring resonance path comprises a pump light source, a Yb-doped optical fiber and a light modulation unit. The pump light source emits a pump light. The Yb-doped optical fiber is coupled with the pump light. The light modulation unit includes a grating pair, a diaphragm and two reflective elements. The grating pair is coupled with the pump light. The diaphragm includes an aperture. The light transmitted by the grating pair partially passes through the aperture and reaches one of the reflective elements to become a reflective light, and the reflective light passes through the aperture and is transmitted through the grating pair and the other reflective element to be coupled back with the ring resonance path.