Patents by Inventor Chih Hsueh
Chih Hsueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948920Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.Type: GrantFiled: August 30, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Chun Hsu, Yan-Zuo Tsai, Chia-Yin Chen, Yang-Chih Hsueh, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20230387112Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.Type: ApplicationFiled: July 26, 2023Publication date: November 30, 2023Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
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Publication number: 20230378327Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.Type: ApplicationFiled: August 8, 2023Publication date: November 23, 2023Inventors: Chen-Wei PAN, Jen-Chih HSUEH, Li-Feng CHU, Chih-Teng LIAO
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Patent number: 11824103Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.Type: GrantFiled: April 23, 2021Date of Patent: November 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Wei Pan, Jen-Chih Hsueh, Li-Feng Chu, Chih-Teng Liao
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Patent number: 11804488Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.Type: GrantFiled: July 20, 2022Date of Patent: October 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
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Publication number: 20230220730Abstract: A safety ladder for mounting between a support surface and a ground surface includes two support assemblies and parallel step members pivoted between the support assemblies. Each support assembly includes first and second support rods each having upper and lower ends. The upper ends of the first support rods of the support assemblies are configured to be pivoted to the support surface. The safety ladder is movable between a use position, in which the lower ends of the first and second support rods of the support assemblies are adapted to simultaneously contact the ground surface, and a storage position, in which the first and second support rods stand substantially perpendicular relative to the ground surface.Type: ApplicationFiled: May 19, 2021Publication date: July 13, 2023Inventors: YA-CHING CHAN, CHIH-HSUEH LIN
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Publication number: 20230120360Abstract: This invention discloses a traditional Chinese medicine, Mu Dan Pi (Moutan radicis cort), that has the potential to be used for the prevention or treatment of cachexia and muscle loss in cancer patients. The composition is a novel therapeutic agent for cachexia.Type: ApplicationFiled: October 13, 2022Publication date: April 20, 2023Applicant: CHINA MEDICAL UNIVERSITYInventors: Hsiang-Wen Lin, Chih-Hsueh Lin, Liang-Yo Yang, Chih-Shiang Chang, Ching-Shih Chen
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Publication number: 20230063851Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Chun Hsu, Yan-Zuo Tsai, Chia-Yin Chen, Yang-Chih Hsueh, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20220406913Abstract: Embodiments include methods and devices which utilize dummy gate profiling to provide a profile of a dummy gate which has narrowing in the dummy gate. The narrowing causes a neck in the dummy gate. When the dummy gate is replaced in a gate replacement process, the necking provides control of an etch-back process. Space is provided between the replacement gate and a subsequently formed self-aligned contact.Type: ApplicationFiled: May 25, 2022Publication date: December 22, 2022Inventors: Hsiu-Ling Chen, Chih-Teng Liao, Jen-Chih Hsueh, Chen-Wei Pan, Yu-Li Lin
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Publication number: 20220359505Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
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Publication number: 20220344497Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Inventors: Chen-Wei PAN, Jen-Chih HSUEH, Li-Feng CHU, Chih-Teng LIAO
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Publication number: 20220307266Abstract: A ventilation assembly (200) includes a frame unit (100) and a cover body (60). The frame unit (100) includes two frame assemblies (10) and two closing plates (30) connected between the frame assemblies (10). Each frame assembly (10) includes two frame seats (11) and outer and inner side plates (12, 13) cooperatively defining a tortuous passage (14). Each frame assembly (10) further includes first and second air vents (15, 16). The cover body (60) is connected to and cooperates with the frame assemblies (10) and the closing plates (30) to define an air chamber (70) configured to communicate with an opening (102) in an upper portion (1) of a building. The first air vent (15) is provided to communicate the air chamber (70) with the tortuous passage (14), and the second air vent (16) is provided to communicate the tortuous passage (14) with the atmosphere.Type: ApplicationFiled: September 15, 2020Publication date: September 29, 2022Inventors: Chih-Hsueh LIN, Ya-Ching CHAN
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Patent number: 11448294Abstract: A linkage mechanism includes a pivoting assembly, a cam, a sliding assembly and at least one linkage. The cam pivots coaxially with the rotating axis of the pivoting assembly. A leaning element is located on one side of the cam. A sliding frame pivots the leaning element and has at least one limiting area. The linkage includes a main body portion, a first linkage portion protruded beyond the limiting area and a second linkage portion. When the pivoting assembly drives the cam to pivot from a first position to a second position, the cam pushes against the leaning element to slide the sliding frame in a first direction relative to a plate, and the limiting area interferes with the first linkage portion of the linkage to rotate the main body portion in a first clock direction to allow the second linkage portion to provide a thrust in a second direction.Type: GrantFiled: January 16, 2020Date of Patent: September 20, 2022Assignee: COMPAL ELECTRONICS, INCInventors: Chin-Hsien Chang, Chih-Hsueh Tsai
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Patent number: 11398477Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.Type: GrantFiled: November 30, 2020Date of Patent: July 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
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Publication number: 20220115545Abstract: A tunnel oxide passivated contact solar cell includes a semiconductor substrate, an emitter film layer, an anti-reflective layer, a first electrode, a tunnel oxide layer, a semiconductor film layer and a second electrode. The semiconductor substrate is a first type doped semiconductor, and the first surface of the semiconductor substrate includes a zigzag structure. The emitter film layer is a second type doped semiconductor film. The anti-reflective layer is provided with a first opening. A part of the first electrode is in the first opening and electrically connected to the emitter film layer. The tunnel oxide layer has a thickness ranging from 1.3 nm to 1.6 nm, the thickness difference measured is less than 4%, and the tunnel oxide layer is made by an atomic layer deposition process. The semiconductor film layer is a first type doped semiconductor. The second electrode is electrically connected to the semiconductor film layer.Type: ApplicationFiled: January 25, 2021Publication date: April 14, 2022Applicant: United Renewable Energy Co., Ltd.Inventors: Chih-Jeng HUANG, Jen-Hao SONG, An-Chih HSUEH
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Publication number: 20210111176Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.Type: ApplicationFiled: November 30, 2020Publication date: April 15, 2021Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
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Patent number: 10915150Abstract: A linkage mechanism includes a pivoting assembly, a cam, a sliding assembly, and a linkage assembly. The cam pivots coaxially with the rotating axis. The sliding assembly is assembled on a plate member and has a leaning surface and a sliding slot. The linkage assembly includes a linkage passing through the sliding slot and a carrier base including at least one bump and fastened to the linkage. When the pivoting assembly drives the cam to pivot from a first position to a second position, the cam pushes against the leaning surface to slide the sliding assembly relative to the plate member in a first direction, and the linkage rotates in the sliding slot to drive the carrier base to move in a second direction, and the bump gradually enters into a cavity of a frame from leaning the frame to move the frame in a third direction.Type: GrantFiled: October 5, 2019Date of Patent: February 9, 2021Assignee: COMPAL ELECTRONICS, INC.Inventors: Chin-Hsien Chang, Chih-Hsueh Tsai
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Publication number: 20210011521Abstract: A linkage mechanism includes a pivoting assembly, a cam, a sliding assembly, and a linkage assembly. The cam pivots coaxially with the rotating axis. The sliding assembly is assembled on a plate member and has a leaning surface and a sliding slot. The linkage assembly includes a linkage passing through the sliding slot and a carrier base including at least one bump and fastened to the linkage. When the pivoting assembly drives the cam to pivot from a first position to a second position, the cam pushes against the leaning surface to slide the sliding assembly relative to the plate member in a first direction, and the linkage rotates in the sliding slot to drive the carrier base to move in a second direction, and the bump gradually enters into a cavity of a frame from leaning the frame to move the frame in a third direction.Type: ApplicationFiled: October 5, 2019Publication date: January 14, 2021Applicant: COMPAL ELECTRONICS, INC.Inventors: Chin-Hsien Chang, Chih-Hsueh Tsai
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Publication number: 20210010576Abstract: A linkage mechanism includes a pivoting assembly, a cam, a sliding assembly and at least one linkage. The cam pivots coaxially with the rotating axis of the pivoting assembly. A leaning element is located on one side of the cam. A sliding frame pivots the leaning element and has at least one limiting area. The linkage includes a main body portion, a first linkage portion protruded beyond the limiting area and a second linkage portion. When the pivoting assembly drives the cam to pivot from a first position to a second position, the cam pushes against the leaning element to slide the sliding frame in a first direction relative to a plate, and the limiting area interferes with the first linkage portion of the linkage to rotate the main body portion in a first clock direction to allow the second linkage portion to provide a thrust in a second direction.Type: ApplicationFiled: January 16, 2020Publication date: January 14, 2021Applicant: COMPAL ELECTRONICS, INC.Inventors: Chin-Hsien Chang, Chih-Hsueh Tsai
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Patent number: 10867831Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.Type: GrantFiled: August 14, 2020Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao, Wen-Chih Chiou