Abstract: A bonding tool for bonding semiconductor dies to a semiconductor wafer is provided. The bonding tool includes a wafer chuck, an edge support, a hard plate, and a buffer layer. The wafer chuck carries the semiconductor wafer and the semiconductor dies placed on the semiconductor wafer. The edge support is disposed on the wafer chuck, the semiconductor wafer and the semiconductor dies are laterally surrounded by the edge support, and a top surface of the edge support substantially levels with surfaces of the semiconductor dies. The hard plate is movably disposed over the semiconductor dies, the edge support and the wafer chuck. The buffer layer is disposed on a bottom surface of the hard plate, and the buffer layer is in contact with the top surface of the edge support and the semiconductor dies when the hard plate moves towards the edge support.

Abstract: A ventilation assembly (200) includes a frame unit (100) and a cover body (60). The frame unit (100) includes two frame assemblies (10) and two closing plates (30) connected between the frame assemblies (10). Each frame assembly (10) includes two frame seats (11) and outer and inner side plates (12, 13) cooperatively defining a tortuous passage (14). Each frame assembly (10) further includes first and second air vents (15, 16). The cover body (60) is connected to and cooperates with the frame assemblies (10) and the closing plates (30) to define an air chamber (70) configured to communicate with an opening (102) in an upper portion (1) of a building. The first air vent (15) is provided to communicate the air chamber (70) with the tortuous passage (14), and the second air vent (16) is provided to communicate the tortuous passage (14) with the atmosphere.

Abstract: In a package device, wherein integrated circuit devices are bonded to a substrate, stress arising from mechanical strain, CTE mismatch, and the like can be alleviated or eliminated by incorporating stress buffering air gaps into a protective material, such as a gap fill oxide. The air gaps can be formed by tuning and changing deposition parameters during the deposition process and/or by tuning the size and placement of adjacent integrated circuit devices in the package, and/or by forming trenches in the protective material prior to the bonding process.

Abstract: A package includes a first die over and bonded to a first side of a second die, where the second die includes a first substrate, a first interconnect structure over the first substrate, a seal ring disposed within the first interconnect structure, first dummy through substrate vias (TSVs) extending through edge regions of the first substrate of the second die and in physical contact with the seal ring, and functional TSVs extending through a central region of the first substrate of the second die.

Abstract: A method includes bonding a device die onto a package component. The device die includes a semiconductor substrate, and a through-via extending into the semiconductor substrate. The method further includes depositing a dielectric liner lining sidewalls of the device die, depositing a dielectric layer on the dielectric liner, and planarizing the dielectric layer and the device die. Remaining portions of the dielectric liner and the dielectric layer form a gap-filling region, and a top end of the through-via is revealed. An implantation process is performed to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer. A redistribution line is formed over and electrically connecting to the through-via.

Abstract: A method includes depositing a dielectric layer on a package component having a first warpage, and performing an implantation process to implant the dielectric layer with a stress modulation dopant. After the implantation process, the package component has a second warpage smaller than the first warpage.

Abstract: A vehicle control device for shell sharing between control modules comprises a first control module and a second control module. The first control module comprises a plurality of first connectors, a first circuit board, and a first controller arranged in a second area of the first circuit board. The second control module comprises a plurality of second connectors, a second circuit board, and a second controller arranged in the fourth area of the second circuit board. By setting the size of the first circuit board and the second circuit board to be consistent, the number and type of the first connectors and the second connectors to be consistent, and the second area of the second circuit board corresponding to the first area of the first circuit board is set, the shell structure of the first control module and the second control module can be shared. A vehicle is also provided.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

Abstract: Disclosed are an intelligent scheduling method and system. The intelligent scheduling method includes the following steps. A work order assignment module is used to assign multiple work orders to one of multiple production lines respectively. A work order form batching module is used to perform a form batch for the work orders assigned to each production line, so that the work orders are divided into multiple work order groups. A work order detailed scheduling module is used to solve for each work order included in each batch of each production line to obtain a schedule plan, wherein the schedule plan includes an assigned production line of each work order and an operation sequence. The schedule plan is sent to an output device.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

Abstract: A die bonding device is provided to pick up a die and place the die on a carrier. The die bonding device includes a pick-and-placer and a vacuum generator. The pick-and-placer includes an adsorption surface, a first channel and a second channel, and the first channel and the second channel are not connected to each other. The vacuum generator includes a first vacuum pump and a second vacuum pump, the first vacuum pump is connected to the first channel via a pipeline, the second vacuum pump is connected to the second channel via another pipeline, the first vacuum pump and the second vacuum pump make the pick-and-placer adsorb the die to the adsorption surface during a vacuum holding period, and the first vacuum pump and the second vacuum pump respectively make the pick-and-placer release the die to the carrier sequentially in a vacuum release period.

Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

Abstract: A safety ladder for mounting between a support surface and a ground surface includes two support assemblies and parallel step members pivoted between the support assemblies. Each support assembly includes first and second support rods each having upper and lower ends. The upper ends of the first support rods of the support assemblies are configured to be pivoted to the support surface. The safety ladder is movable between a use position, in which the lower ends of the first and second support rods of the support assemblies are adapted to simultaneously contact the ground surface, and a storage position, in which the first and second support rods stand substantially perpendicular relative to the ground surface.

Abstract: This invention discloses a traditional Chinese medicine, Mu Dan Pi (Moutan radicis cort), that has the potential to be used for the prevention or treatment of cachexia and muscle loss in cancer patients. The composition is a novel therapeutic agent for cachexia.

Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.

Abstract: Embodiments include methods and devices which utilize dummy gate profiling to provide a profile of a dummy gate which has narrowing in the dummy gate. The narrowing causes a neck in the dummy gate. When the dummy gate is replaced in a gate replacement process, the necking provides control of an etch-back process. Space is provided between the replacement gate and a subsequently formed self-aligned contact.