Abstract: A system open testing method is provided. Firstly, a system to be tested having at least an ESD protection unit, a signal input pad, a first voltage level end, and a second voltage level end is provided, wherein the first voltage level end and the second voltage level end are utilized for accessing electric power, the ESD protection unit has one end coupled to the signal input pad and the other end coupled to the first voltage level end. Afterward, a diode is connected to the signal input pad, and the conducting direction of the diode is opposite to that of the interior diode in the ESD circuit. Thereafter, a testing signal is send through the diode to the system.

Abstract: The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of material. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.

Abstract: Systems and/or methods that provide for the accuracy of address translations in a memory system that decouples the system address from the physical address. Address-modifying transactions are recorded in a non-volatile write buffer to couple the last-in-time translation physical address/location with the current translated physical location/address. In addition, integrity check protection may be applied to the translation and to the written data to limit the amount of data that may be lost in the event of a failure/error occurring during the write operation. Transaction recording and integrity check protection allows for recovery of write operations that may not have fully completed due to the failure/error.

Abstract: Systems and methods for improving the performance and reliability of flash memory solid state drive devices are described herein. A flash memory array component stores data. A memory hierarchy component transfers data between the host and the flash memory array component. The memory hierarchy component includes a level one (“L1”) cache coupled to a merge buffer, the flash memory array component, and the host. The merge buffer is coupled to the flash memory array component. The L1 cache and merge buffer include volatile memory, and the host is coupled to the merge buffer and flash memory array component. The memory hierarchy component includes a write component and a read component. The write component writes data to at least one of the L1 cache, merge buffer, or flash memory array component. The read component reads data from at least one of the L1 cache, merge buffer, or flash memory array component.

Abstract: Systems and/or methods that provide for the accuracy of address translations in a memory system that decouples the system address from the physical address. Address-modifying transactions are recorded in a non-volatile write buffer to couple the last-in-time translation physical address/location with the current translated physical location/address. In addition, integrity check protection may be applied to the translation and to the written data to limit the amount of data that may be lost in the event of a failure/error occurring during the write operation. Transaction recording and integrity check protection allows for recovery of write operations that may not have fully completed due to the failure/error.

Abstract: The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of4terial. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.

Abstract: A smart-tag housing and method for securing a dedicated data card affixed to a SMIF-pod. A molded housing package for holding a data card for communication with a two-way receiver/transmitter mounted on a workstation, the smart-tag is a small battery operated microcomputer with an LCD for a two-way electro-magnetic communications. The smart-tag housing includes a battery compartment, a battery compartment cover. A retaining plate is affixed to a side of the pod using double-sided adhesive tape. The smart-tag is demountably secured to the retaining plate with a slidable self locking plate. The self locking plate is unlocked with a key that is provided only to authorized personnel.

Abstract: An FFT circuit is implemented using a radix-4 butterfly element and a partitioned memory for storage of a prescribed number of data values. The radix-4 butterfly element is configured for performing an FFT operation in a prescribed number of stages, each stage including a prescribed number of in-place computation operations relative to the prescribed number of data values. The partitioned memory includes a first memory portion and a second memory portion, and the data values for the FFT circuit are divided equally for storage in the first and second memory portions in a manner that ensures that each in-place computation operation is based on retrieval of an equal number of data values retrieved from each of the first and second memory portions.

Abstract: A smart-tag housing and method for securing a dedicated data card affixed to a SMIF-pod. A molded housing package for holding a data card for communication with a two-way receiver/transmitter mounted on a workstation, the smart-tag is a small battery operated microcomputer with an LCD for a two-way electromagnetic communications. The smart-tag housing includes a battery compartment, a battery compartment cover. A retaining plate is affixed to a side of the pod using double-sided adhesive tape. The smart-tag is demountably secured to the retaining plate with a slidable self locking plate. The self locking plate is unlocked with a key that is provided only to authorized personnel.

Abstract: The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric layer contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of material. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.

Abstract: An OFDM receiver configured for measuring frequency error based on comparing prescribed pilot tones from a prescribed group of consecutive symbols in a received OFDM signal. A complex conjugate generator is configured for generating complex conjugates of the prescribed pilot tones of a first subgroup of the consecutive symbols. A multiplier is configured for generating a complex pilot product, for each symbol subgroup position, by multiplying the pilot tones of a second subgroup symbol at the corresponding symbol subgroup position with the respective complex conjugates of the first subgroup symbol at the corresponding symbol subgroup position. A complex summation circuit sums the complex pilot products of the symbol subgroup positions to obtain an accumulated complex value. A error calculator calculates the frequency error from the accumulated complex value for use in correcting frequency offset.

Abstract: A deinterleaver module in an OFDM wireless transceiver includes partitioned memory banks for storage of code word fragments from an interleaved data stream, each code word fragment associated with a prescribed subcarrier frequency. Each code word fragment includes a prescribed number of code word bits based on a prescribed modulation of the interleaved data stream, and the code word bits for each code word fragment are written into respective selected locations of the corresponding memory bank based on the prescribed modulation and the corresponding prescribed subcarrier frequency. The deinterleaver module outputs deinterleaved data from the memory banks based on parallel output of the respective stored code word bits from a selected address of the memory banks.

Abstract: The present invention generally relates to provide a fabrication method for forming a flash memory device provided with an adjustable sharp end structure of the floating gate. While the present invention utilizes the dielectric spacer to form the L-shaped floating gate provided with a sharp end structure, the present invention adjust the thickness of the polysilicon layer and the dielectric layer covering on the polysilicon layer surface to adjust the position of the dielectric spacer so as to change the position of the sharp end structure of the L-shaped floating gate and to enhance the ability of erasing control of the flash memory and to simultaneously form a stable and easily controlled channel length and the sharp end structure for point discharging.

Abstract: The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric layer is formed along the approximately vertical surface of the floating gate and the dielectric spacer and a lateral portion of the second dielectric layer laterally extends over the substrate adjacent the floating gate. A control gate is formed on the lateral portion of the second dielectric layer that laterally extends over the substrate. The control gate is formed on the lateral portion of the second dielectric layer.

Abstract: The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric layer is formed along the approximately vertical surface of the floating gate and the dielectric spacer and a lateral portion of the second dielectric layer laterally extends over the substrate adjacent the floating gate. A control gate is formed on the lateral portion of the second dielectric layer that laterally extends over the substrate. The control gate is formed on the lateral portion of the second dielectric layer.

Abstract: A semiconductor wafer includes a plurality of sensors. Each of the sensors has a field oxide transistor, and a detecting circuit electrically connected to the field oxide transistor for detecting if the field oxide transistor is switched on or off and generating corresponding detecting signals. The field oxide of a different field oxide transistor has a different thickness. Each field oxide transistor is coupled to a corresponding detecting circuit for detecting radiation impinging on the semiconductor wafer.

Abstract: A view tank including an upper partition plate and a lower partition plate dividing the tank body into an upper section, a middle section, and a lower section. The walls of the middle section are transparent and openable for planting purposes. The lower section is a water storage section, and water is pumped to a fog generating box for generating fog. Excessive water flows down from the upper portion of the middle section. The upper section has a light for illuminating the middle section, and a fan for blowing the hot air in the upper and middle sections to the outer rim of the transparent walls of the middle section so as to remove water moisture on the walls. The respective walls of the three sections may be fabricated into integral units which are then assembled as a whole.

Abstract: A method of genetically engineering a cell line capable of detecting bioactive cytokines or growth factors is provided. Cells lines produced by this method and methods of using these cell lines to detect bioactive cytokines or growth factors in a biological fluid are also provided.