Abstract: An anomaly detection device based on a generative adversarial network architecture, which uses the single-type training data composed of multiple normal signals to train an anomaly detection model. The anomaly detection device includes an encoder, a generator, a discriminator, and a random vector generator. In the training phase of anomaly detection model, the random latent vectors generated by the random vector generator are sequentially input to a generator to generate the synthesized signals with the same dimension as the normal signals. The synthesized signals are sequentially input into a discriminator to output the corresponding discriminant values. When the corresponding discriminant values are under the predetermined threshold, the corresponding synthesized signals are selected as the anomalous class training data, and the real normal signals are selected as the normal class training data.

Abstract: In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a semiconductor layer disposed over a substrate, and the semiconductor layer has a first end and a second end opposite the first end. The structure further includes an epitaxial feature disposed over the substrate, and the epitaxial feature is electrically connected to the first end of the semiconductor layer. The structure further includes a first dielectric layer disposed over the substrate, and the first dielectric layer is in contact with the second end of the semiconductor layer. The structure further includes a contact etch stop layer disposed on and in contact with the first dielectric layer and an interlayer dielectric layer disposed on and in contact with the contact etch stop layer.

Abstract: In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

Abstract: A static random access memory (SRAM) cell includes a first gate and a second gate each extending in a first direction. A first gap separates the first gate from the second gate in the first direction. The SRAM cell includes a Vcc contact extending in the first direction. A second gap separates the Vcc contact and the first gate in a second direction perpendicular to the first direction. No segment of the Vcc contact overlaps with the first gap in the first direction. The SRAM cell includes a Vss contact extending in the first direction. A third gap separates the Vss contact from the first gate in the second direction. A segment of the Vss contact is disposed to the first gap. The Vss contact is smaller than the Vcc contact in the second direction.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region of a first conductivity type. The semiconductor device structure also includes a first fin structure and an adjacent second fin structure formed in and protruding from the first well region. The semiconductor device structure also includes a first isolation structure formed in the first well region between the first fin structure and the second fin structure. A first sidewall surface of the first fin structure faces to a second sidewall surface of the second fin structure. The first sidewall surface and the second sidewall surface each extend along at least two directions from a bottom of the first isolation structure to a top of the first isolation structure.

Abstract: A static random access memory (SRAM) cell includes a first gate and a second gate each extending in a first direction. A first gap separates the first gate from the second gate in the first direction. The SRAM cell includes a Vcc contact extending in the first direction. A second gap separates the Vcc contact and the first gate in a second direction perpendicular to the first direction. No segment of the Vcc contact overlaps with the first gap in the first direction. The SRAM cell includes a Vss contact extending in the first direction. A third gap separates the Vss contact from the first gate in the second direction. A segment of the Vss contact is disposed to the first gap. The Vss contact is smaller than the Vcc contact in the second direction.

Abstract: A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.

Abstract: Methods and structures for the co-optimization of memory and logic devices. A device includes a substrate having a first region and a second region. The device may include a first gate structure disposed in the first region and a second gate structure disposed in the second region. The device may further include a first source/drain feature disposed adjacent to the first gate structure and a second source/drain feature disposed adjacent to the second gate structure. A first top surface of the first source/drain feature and a second top surface of the second source/drain feature are substantially level. A first bottom surface of the first source/drain feature is a first distance away from the first top surface, and a second bottom surface of the second source/drain feature is a second distance away from the second top surface. In some cases, the second distance is greater than the first distance.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and an adjacent second fin structure protruding from the semiconductor substrate and an isolation structure formed in the semiconductor substrate and in direct contact with the first fin structure and the second fin structure. The first fin structure and the second fin structure each include a first portion protruding above a top surface of the isolation structure, a second portion in direct contact with a bottom surface of the first portion, and a third portion extending from a bottom of the second portion. A top width of the third portion is different than a bottom width of the third portion and a bottom width of the second portion.

Abstract: A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.

Abstract: An actuating system for a window shade includes a first rotary axle rotatable for displacing a bottom part, a second rotary axle rotatable for displacing an intermediate rail, and a limiting mechanism including a first and a second sliding part respectively linked movably to the first and second rotary axle. The first sliding part slides in a first direction when the first rotary axle rotates for lowering the bottom part and in a second direction when the first rotary axle rotates for raising the bottom part. The second sliding part slides in the first direction when the second rotary axle rotates for lowering the intermediate rail and in the second direction when the second rotary axle rotates for raising the intermediate rail. The first sliding part is prevented from sliding in the second direction via a contact between the first sliding part and the second sliding part.

Abstract: A static random access memory (SRAM) cell includes a first gate and a second gate each extending in a first direction. A first gap separates the first gate from the second gate in the first direction. The SRAM cell includes a Vcc contact extending in the first direction. A second gap separates the Vcc contact and the first gate in a second direction perpendicular to the first direction. No segment of the Vcc contact overlaps with the first gap in the first direction. The SRAM cell includes a Vss contact extending in the first direction. A third gap separates the Vss contact from the first gate in the second direction. A segment of the Vss contact is disposed to the first gap. The Vss contact is smaller than the Vcc contact in the second direction.

Abstract: An anomaly detection device based on a generative adversarial network architecture, which uses the single-type training data composed of multiple normal signals to train an anomaly detection model. The anomaly detection device includes an encoder, a generator, a discriminator, and a random vector generator. In the training phase of anomaly detection model, the random latent vectors generated by the random vector generator are sequentially input to a generator to generate the synthesized signals with the same dimension as the normal signals. The synthesized signals are sequentially input into a discriminator to output the corresponding discriminant values. When the corresponding discriminant values are under the predetermined threshold, the corresponding synthesized signals are selected as the anomalous class training data, and the real normal signals are selected as the normal class training data.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and an adjacent second fin structure protruding from the semiconductor substrate and an isolation structure formed in the semiconductor substrate and in direct contact with the first fin structure and the second fin structure. The first fin structure and the second fin structure each include a first portion protruding above a top surface of the isolation structure, a second portion in direct contact with a bottom surface of the first portion, and a third portion extending from a bottom of the second portion. A top width of the third portion is different than a bottom width of the third portion and a bottom width of the second portion.

Abstract: A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.

Abstract: A SRAM structure includes a first SRAM cell, a second SRAM cell arranged in mirror symmetry with the first SRAM cell along a first direction, a third SRAM cell arranged in mirror symmetry with the first SRAM cell along a second direction perpendicular to the first direction, and a fourth SRAM cell arranged in mirror symmetry with the third SRAM cell along the first direction and arranged in mirror symmetry with the second SRAM cell along the second direction. Each of SRAM cells includes a first and a second pull-down transistor. The SRAM structure further includes a contact bar extending in the second direction to sources of the second pull-down transistors of the first and third SRAM cells and extending in a third direction opposite to the second direction to sources of the second pull-down transistors of the second and fourth SRAM cells.

Abstract: In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first and second well regions with different conductivity types in a semiconductor substrate. A well interface is formed between the first and second well regions. The method also includes patterning the semiconductor substrate to form a first fin structure in the first well region, a second fin structure in the second well region, and a first trench between the first and second fin structures. The first trench exposes the well interface in the semiconductor substrate. The method further includes forming insulating spacers on opposite sidewalls of the first trench and etching the semiconductor substrate below the first trench using the insulating spacers as an etch mask, to form a second trench below the first trench. In addition, the method includes filling the first and second trenches with an insulating material.