Patents by Inventor Chih-Hung Hsieh

Chih-Hung Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220246107
    Abstract: A gate driving circuit includes a bootstrapping circuit, a pre-charge circuit, and an output control circuit. The bootstrapping circuit is composed of a bootstrapping capacitor and a transistor. A first terminal of the bootstrapping capacitor has a first voltage during a first duration. The pre-charge circuit is connected to the first terminal of the bootstrapping capacitor. The pre-charge circuit boosts the first terminal of the bootstrapping capacitor from the first voltage to a second voltage during a second duration. The bootstrapping circuit boosts the first terminal of the bootstrapping capacitor from the second voltage to a third voltage during a third duration. The output control circuit is connected to the first terminal of the bootstrapping capacitor. The output control circuit boosts the first terminal of the bootstrapping capacitor from the third voltage to a fourth voltage during a fourth duration.
    Type: Application
    Filed: March 12, 2021
    Publication date: August 4, 2022
    Inventors: Po-Lun CHEN, Chun-Ta CHEN, Chih-Lin LIAO, Fu-Cheng WEI, Po-Tsun LIU, Guang-Ting ZHENG, Ping-Hung HSIEH
  • Patent number: 11378843
    Abstract: A display device is provided. The display device includes a substrate and a plurality of pixels disposed on the substrate. One of the pixels includes a color conversion layer, a dielectric layer disposed on the color conversion layer, and a light filter layer disposed on the dielectric layer. The display device also includes a first light shielding layer, a second light shielding layer, and a plurality of light emitting diodes. The first light shielding layer defines a plurality of openings, wherein at least one of the color conversion layer, the dielectric layer and the light filter layer is disposed in the openings. The second light shielding layer is disposed on the substrate and at least partially overlapped with the first light shielding layer. The second light shielding layer defines another plurality of openings, and the light emitting diodes are disposed in the another openings.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: July 5, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Yi-An Chen, Kuan-Hung Kuo, Tsau-Hua Hsieh, Ming-I Chao, Shu-Ming Kuo, Chin-Lung Ting, Chih-Yung Hsieh
  • Publication number: 20220156580
    Abstract: An anomaly detection device based on a generative adversarial network architecture, which uses the single-type training data composed of multiple normal signals to train an anomaly detection model. The anomaly detection device includes an encoder, a generator, a discriminator, and a random vector generator. In the training phase of anomaly detection model, the random latent vectors generated by the random vector generator are sequentially input to a generator to generate the synthesized signals with the same dimension as the normal signals. The synthesized signals are sequentially input into a discriminator to output the corresponding discriminant values. When the corresponding discriminant values are under the predetermined threshold, the corresponding synthesized signals are selected as the anomalous class training data, and the real normal signals are selected as the normal class training data.
    Type: Application
    Filed: December 29, 2020
    Publication date: May 19, 2022
    Inventors: Yi-Hsiang CHAO, Chih-Hung HSIEH, Ming-Yu SHIH
  • Publication number: 20220149039
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and an adjacent second fin structure protruding from the semiconductor substrate and an isolation structure formed in the semiconductor substrate and in direct contact with the first fin structure and the second fin structure. The first fin structure and the second fin structure each include a first portion protruding above a top surface of the isolation structure, a second portion in direct contact with a bottom surface of the first portion, and a third portion extending from a bottom of the second portion. A top width of the third portion is different than a bottom width of the third portion and a bottom width of the second portion.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Tien-Shao CHUANG, Kuang-Cheng TAI, Chun-Hung CHEN, Chih-Hung HSIEH, Kuo-Hua PAN, Jhon-Jhy LIAW
  • Publication number: 20220084888
    Abstract: A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.
    Type: Application
    Filed: November 26, 2021
    Publication date: March 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Chen, Chih-Hung Hsieh, Jhon-Jhy Liaw
  • Patent number: 11276696
    Abstract: A SRAM structure includes a first SRAM cell, a second SRAM cell arranged in mirror symmetry with the first SRAM cell along a first direction, a third SRAM cell arranged in mirror symmetry with the first SRAM cell along a second direction perpendicular to the first direction, and a fourth SRAM cell arranged in mirror symmetry with the third SRAM cell along the first direction and arranged in mirror symmetry with the second SRAM cell along the second direction. Each of SRAM cells includes a first and a second pull-down transistor. The SRAM structure further includes a contact bar extending in the second direction to sources of the second pull-down transistors of the first and third SRAM cells and extending in a third direction opposite to the second direction to sources of the second pull-down transistors of the second and fourth SRAM cells.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Hsieh, Yu-Min Liao, Jhon-Jhy Liaw
  • Publication number: 20220059351
    Abstract: In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.
    Type: Application
    Filed: November 1, 2021
    Publication date: February 24, 2022
    Inventors: Chun-Hung CHEN, Chih-Hung HSIEH, Jhon Jhy LIAW
  • Patent number: 11251069
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first and second well regions with different conductivity types in a semiconductor substrate. A well interface is formed between the first and second well regions. The method also includes patterning the semiconductor substrate to form a first fin structure in the first well region, a second fin structure in the second well region, and a first trench between the first and second fin structures. The first trench exposes the well interface in the semiconductor substrate. The method further includes forming insulating spacers on opposite sidewalls of the first trench and etching the semiconductor substrate below the first trench using the insulating spacers as an etch mask, to form a second trench below the first trench. In addition, the method includes filling the first and second trenches with an insulating material.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun Lin, Tien-Shao Chuang, Kuang-Cheng Tai, Chun-Hung Chen, Chih-Hung Hsieh, Kuo-Hua Pan, Jhon-Jhy Liaw
  • Patent number: 11195760
    Abstract: A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Chen, Chih-Hung Hsieh, Jhon-Jhy Liaw
  • Publication number: 20210351038
    Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. The first gate electrode layer is in contact with a side wall of the separation plug.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Inventor: Chih-Hung HSIEH
  • Patent number: 11164746
    Abstract: In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hung Chen, Chih-Hung Hsieh, Jhon Jhy Liaw
  • Patent number: 11075082
    Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. The first gate electrode layer is in contact with a side wall of the separation plug.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chih-Hung Hsieh
  • Publication number: 20210172246
    Abstract: An actuating system for a window shade includes a first rotary axle rotatable for displacing a bottom part, a second rotary axle rotatable for displacing an intermediate rail, and a limiting mechanism including a first and a second sliding part respectively linked movably to the first and second rotary axle. The first sliding part slides in a first direction when the first rotary axle rotates for lowering the bottom part and in a second direction when the first rotary axle rotates for raising the bottom part. The second sliding part slides in the first direction when the second rotary axle rotates for lowering the intermediate rail and in the second direction when the second rotary axle rotates for raising the intermediate rail. The first sliding part is prevented from sliding in the second direction via a contact between the first sliding part and the second sliding part.
    Type: Application
    Filed: December 3, 2020
    Publication date: June 10, 2021
    Applicant: Teh Yor Co., Ltd.
    Inventors: Chung-Chen HUANG, Chih Hung HSIEH
  • Publication number: 20210043635
    Abstract: A SRAM structure includes a first SRAM cell, a second SRAM cell arranged in mirror symmetry with the first SRAM cell along a first direction, a third SRAM cell arranged in mirror symmetry with the first SRAM cell along a second direction perpendicular to the first direction, and a fourth SRAM cell arranged in mirror symmetry with the third SRAM cell along the first direction and arranged in mirror symmetry with the second SRAM cell along the second direction. Each of SRAM cells includes a first and a second pull-down transistor. The SRAM structure further includes a contact bar extending in the second direction to sources of the second pull-down transistors of the first and third SRAM cells and extending in a third direction opposite to the second direction to sources of the second pull-down transistors of the second and fourth SRAM cells.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hung HSIEH, Yu-Min LIAO, Jhon-Jhy LIAW
  • Publication number: 20200411363
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first and second well regions with different conductivity types in a semiconductor substrate. A well interface is formed between the first and second well regions. The method also includes patterning the semiconductor substrate to form a first fin structure in the first well region, a second fin structure in the second well region, and a first trench between the first and second fin structures. The first trench exposes the well interface in the semiconductor substrate. The method further includes forming insulating spacers on opposite sidewalls of the first trench and etching the semiconductor substrate below the first trench using the insulating spacers as an etch mask, to form a second trench below the first trench. In addition, the method includes filling the first and second trenches with an insulating material.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Tien-Shao CHUANG, Kuang-Cheng TAI, Chun-Hung CHEN, Chih-Hung HSIEH, Kuo-Hua PAN, Jhon-Jhy LIAW
  • Patent number: 10818675
    Abstract: SRAM structures are provided. A SRAM structure includes multiple SRAM cells arranged in multiple rows and multiple columns. A first SRAM cell is adjacent to a second SRAM cell in the same row. A third SRAM cell is adjacent to the first SRAM cell in the same column. A fourth SRAM cell is adjacent to the second SRAM in the same column. A contact plug is positioned between the first, second, third and fourth SRAM cells. A VSS line is electrically coupled to the first, second, third and fourth SRAM cells through the contact plug. The contact plug is free of the barrier layer.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hung Hsieh, Yu-Min Liao, Jhon-Jhy Liaw
  • Patent number: 10790184
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region and a second well region that have different conductivity types and are adjacent to each other. A first fin structure protrudes from the semiconductor substrate and is formed in the first well region. A second fin structure protrudes from the semiconductor substrate and is formed in the second well region and adjacent to the first fin structure. A first multi-step isolation structure that includes a first isolation portion is formed between the first fin structure and the second fin structure. A second isolation portion extends from the bottom surface of the first isolation portion. The second isolation portion has a top width that is narrower than the bottom width of the first isolation portion.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ta-Chun Lin, Tien-Shao Chuang, Kuang-Cheng Tai, Chun-Hung Chen, Chih-Hung Hsieh, Kuo-Hua Pan, Jhon-Jhy Liaw
  • Patent number: 10742668
    Abstract: A network attack pattern determination apparatus, method, and non-transitory computer readable storage medium thereof are provided. The apparatus is stored with several attack patterns and access records. Each access record includes a network address, time stamp, and access content. Each attack pattern corresponds to at least one attack access relation. Each attack access relation is defined by a network address and access content. The apparatus retrieves several attack records according to at least one attack address. The network address of each attack record is one of the attack address(s). The apparatus divides the attack records into several groups according to the time stamps and performs the following operations for each group: (a) creating at least one access relation for each attack address included in the group and (b) determining that the group corresponds to one of the attack patterns according to the at least one access relation of the group.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: August 11, 2020
    Assignee: Institute For Information Industry
    Inventors: Chia-Min Lai, Ching-Hao Mao, Chih-Hung Hsieh, Te-En Wei, Chi-Ping Lai
  • Patent number: 10714488
    Abstract: A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns is formed over the dielectric structure. The contact-line-blocking patterns are formed using three or more lithography masks. A plurality of trenches is formed in the dielectric structure. The contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns. The trenches are filled with a conductive material to form a plurality of contact lines of the SRAM device.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Han Huang, Chih-Hung Hsieh
  • Publication number: 20200219773
    Abstract: A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.
    Type: Application
    Filed: March 19, 2020
    Publication date: July 9, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hung Chen, Chih-Hung Hsieh, Jhon-Jhy Liaw