Abstract: In a method of manufacturing a semiconductor device, a first FinFET including a first fin structure, a first gate electrode structure disposed over the first fin structure and a first source/drain region is formed. A second FinFET including one second fin structure, a second gate electrode structure disposed over the second fin structure and a second source/drain region is formed. A first epitaxial layer is formed on the first fin structure in the first source/drain region, and a second epitaxial layer is formed on the second fin structure in the second source/drain region. A width of the first fin structure is smaller than a width of the second fin structure.

Abstract: An attacking node detection apparatus, method, and computer program product thereof are provided. The attacking node detection apparatus is stored with a plurality of access records of an application, wherein each access record includes a network address of a host and an access content. The attacking node detection apparatus filters the access records into a plurality of filtered access records according to a predetermined rule so that the access content of each filtered access record conforms to the predetermined rule. The attacking node detection apparatus creates at least one access relation of each of the network addresses according to the filtered access records, wherein each access relation is defined by one of the network addresses and one of the access contents. The attacking node detection apparatus identifies a specific network address as an attacking node according to the access relations.

Abstract: A network attack pattern determination apparatus, method, and non-transitory computer readable storage medium thereof are provided. The apparatus is stored with several attack patterns and access records. Each access record includes a network address, time stamp, and access content. Each attack pattern corresponds to at least one attack access relation. Each attack access relation is defined by a network address and access content. The apparatus retrieves several attack records according to at least one attack address. The network address of each attack record is one of the attack address(s). The apparatus divides the attack records into several groups according to the time stamps and performs the following operations for each group: (a) creating at least one access relation for each attack address included in the group and (b) determining that the group corresponds to one of the attack patterns according to the at least one access relation of the group.

Abstract: A read-only memory (ROM) structure is provided. The ROM device structure includes an active region formed over a substrate and a first group of word lines formed over the active region. The first group of word lines includes at least two word lines. The ROM device structure includes a second group of word lines formed on the active region, and the second group of word lines includes at least two word lines. The ROM device structure further includes an isolation line between the first group of word lines and the second group of word lines and over the active region. The first group of word lines, the second group of word lines, and the isolation line are formed in a second metal layer.

Abstract: A backlight module includes a back board, an illumination assembly, a supporting component and a frame. The illumination assembly is disposed on the back board. The supporting component includes a base, a first extending plate and a second extending plate. The base is disposed on the back board. Both of the first extending plate and the second extending plate stand on the base and extend along an axial direction of the base so that the first extending plate and the second extending plate are at a first angle and a second angle relative to the base, respectively. The first extending plate is located between the second extending plate and the illumination assembly. The frame is disposed on the supporting component, and the illumination assembly is located between the frame and the back board.

Abstract: A read-only memory (ROM) structure is provided. The ROM device structure includes an active region formed over a substrate and a first group of word lines formed over the active region. The first group of word lines includes at least two word lines. The ROM device structure includes a second group of word lines formed on the active region, and the second group of word lines includes at least two word lines. The ROM device structure further includes an isolation line between the first group of word lines and the second group of word lines and over the active region. The first group of word lines, the second group of word lines, and the isolation line are formed in a second metal layer.

Abstract: In a method of manufacturing a semiconductor device, a first FinFET including a first fin structure, a first gate electrode structure disposed over the first fin structure and a first source/drain region is formed. A second FinFET including one second fin structure, a second gate electrode structure disposed over the second fin structure and a second source/drain region is formed. A first epitaxial layer is formed on the first fin structure in the first source/drain region, and a second epitaxial layer is formed on the second fin structure in the second source/drain region. A width of the first fin structure is smaller than a width of the second fin structure.

Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. The first gate electrode layer is in contact with a side wall of the separation plug.

Abstract: The instant disclosure illustrates a system and method for information security management based on application level log analysis. The system and method for information security management involve analyzing a plurality of application level logs of a user and modeling the continuative behaviors of the user. Furthermore, the system and method for information security management include the selection of models according to different environmental contexts, thereby efficiently determining whether the user has had an abnormal behavior occur.

Abstract: In a method of manufacturing an SRAM, first dummy patterns are formed over a substrate, on which a first to a third mask layer are formed. Intermediate dummy patterns are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the intermediate dummy patterns. The third mask layer is patterned by using the intermediate dummy patterns, by which the second mask layer is patterned, thereby forming second dummy patterns. Sidewall spacer layers are formed on sidewalls of the second dummy patterns. The second dummy patterns are removed, thereby leaving the sidewall spacer layers as hard mask patterns over the substrate, by which the first mask layer is patterned. The substrate is patterned by using the patterned first mask layer. Each of the plurality of SRAM cells is defined by a cell boundary, within which only two first dummy patterns are included.

Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. The first gate electrode layer is in contact with a side wall of the separation plug.

Abstract: A backlight module includes a back board, an illumination assembly, a supporting component and a frame. The illumination assembly is disposed on the back board. The supporting component includes a base, a first extending plate and a second extending plate. The base is disposed on the back board. Both of the first extending plate and the second extending plate stand on the base and extend along an axial direction of the base so that the first extending plate and the second extending plate are at a first angle and a second angle relative to the base, respectively. The first extending plate is located between the second extending plate and the illumination assembly. The frame is disposed on the supporting component, and the illumination assembly is located between the frame and the back board.

Abstract: Devices and methods for interpreting an input key from a keystroke are disclosed. In an implementation, the method includes displaying a keyboard including keys. The method also includes defining targets on the keyboard. Each one of the targets is associated with one of the keys, an area of the keyboard, and a swipe direction. Each one of the keys is associated with at least two of the targets. The method also includes determining a location and a swipe direction of the keystroke, and comparing the location of the keystroke with the areas associated with at least some of the targets. The method also includes comparing the swipe direction of the keystroke with the swipe directions associated with at least some of the targets, and defining the input key based on the comparisons of the location of the keystroke and the swipe direction of the keystroke with the targets.

Abstract: Devices and methods for interpreting an input key from a keystroke are disclosed. In an implementation, the method includes displaying a keyboard including keys. The method also includes defining targets on the keyboard. Each one of the targets is associated with one of the keys, an area of the keyboard, and a swipe direction. Each one of the keys is associated with at least two of the targets. The method also includes determining a location and a swipe direction of the keystroke, and comparing the location of the keystroke with the areas associated with at least some of the targets. The method also includes comparing the swipe direction of the keystroke with the swipe directions associated with at least some of the targets, and defining the input key based on the comparisons of the location of the keystroke and the swipe direction of the keystroke with the targets.

Abstract: Devices and methods for interpreting an input key from a keystroke are disclosed. In an implementation, the method includes displaying a keyboard including keys. The method also includes defining targets on the keyboard. Each one of the targets is associated with one of the keys, an area of the keyboard, and a swipe direction. Each one of the keys is associated with at least two of the targets. The method also includes determining a location and a swipe direction of the keystroke, and comparing the location of the keystroke with the areas associated with at least some of the targets. The method also includes comparing the swipe direction of the keystroke with the swipe directions associated with at least some of the targets, and defining the input key based on the comparisons of the location of the keystroke and the swipe direction of the keystroke with the targets.

Abstract: A semiconductor device includes a semiconductor substrate; a gate dielectric layer disposed on the semiconductor substrate; a gate conductive layer doped with impurities selected from nitrogen, carbon, silicon, germanium, fluorine, oxygen, helium, neon, xenon or a combination thereof on the gate dielectric layer; and source/drain doped regions formed adjacent to the gate conductive layer in the semiconductor substrate, wherein the source and drain doped regions are substantially free of the impurities doped into the gate conductive layer. These impurities reduce the diffusion rates of the N-type of P-type dopants in the gate conductive layer, thereby improving the device performance.

Abstract: The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes four sets of cascaded n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), each set of cascaded NMOSFETs having a pull-down device and a pass-gate device; and a first and second pull-up devices (PU1 and PU2) configured with the four pull-down devices to form two cross-coupled inverters, wherein two of the pass-gate devices are configured to form a first port and another two of the pass-gate devices are configured to form a second port.

Abstract: An apparatus for segregating electronic components that engages and stops each of a plurality of electronic packages passing down a singulation tube is disclosed. In addition, the segregating apparatus is cable of segregating the electronic packages even though some of them had been linked together during the sealing process. The segregating apparatus includes a first swing arm to clip a electronic component, a second swing arm to clip another electronic component, and a third swing arm to depart the two electronic components, where all of components of the segregating apparatus are driven by a single driving force, reducing the size of the apparatus and the time needed for the segregating process.

Abstract: The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes four sets of cascaded n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), each set of cascaded NMOSFETs having a pull-down device and a pass-gate device; and a first and second pull-up devices (PU1 and PU2) configured with the four pull-down devices to form two cross-coupled inverters, wherein two of the pass-gate devices are configured to form a first port and another two of the pass-gate devices are configured to form a second port.

Abstract: In the present invention, a feeding apparatus comprising a plurality of feeding mechanisms is provided. The feeding apparatus comprises a power source, a base, a rotating axle, a plurality of feeding mechanisms, a plurality of connecting units and a plurality of fixing units. The power source is driven to rotate the rotating axle, and then the feeding mechanisms are rotated by the rotating axle to proceed feeding process. In addition, the rotation of each of the feeding mechanisms is controlled by the connecting units and the fixing units. However, the feeding mechanisms can be rotated together or individually to proceed feeding process. Therefore, the production capacity is increased by the feeding apparatus, as well as the cost is reduced by decreasing power needed.