Patents by Inventor Chih-Hung Hsieh
Chih-Hung Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220084888Abstract: A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.Type: ApplicationFiled: November 26, 2021Publication date: March 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hung Chen, Chih-Hung Hsieh, Jhon-Jhy Liaw
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Patent number: 11276696Abstract: A SRAM structure includes a first SRAM cell, a second SRAM cell arranged in mirror symmetry with the first SRAM cell along a first direction, a third SRAM cell arranged in mirror symmetry with the first SRAM cell along a second direction perpendicular to the first direction, and a fourth SRAM cell arranged in mirror symmetry with the third SRAM cell along the first direction and arranged in mirror symmetry with the second SRAM cell along the second direction. Each of SRAM cells includes a first and a second pull-down transistor. The SRAM structure further includes a contact bar extending in the second direction to sources of the second pull-down transistors of the first and third SRAM cells and extending in a third direction opposite to the second direction to sources of the second pull-down transistors of the second and fourth SRAM cells.Type: GrantFiled: October 26, 2020Date of Patent: March 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hung Hsieh, Yu-Min Liao, Jhon-Jhy Liaw
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Publication number: 20220059351Abstract: In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.Type: ApplicationFiled: November 1, 2021Publication date: February 24, 2022Inventors: Chun-Hung CHEN, Chih-Hung HSIEH, Jhon Jhy LIAW
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Patent number: 11251069Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first and second well regions with different conductivity types in a semiconductor substrate. A well interface is formed between the first and second well regions. The method also includes patterning the semiconductor substrate to form a first fin structure in the first well region, a second fin structure in the second well region, and a first trench between the first and second fin structures. The first trench exposes the well interface in the semiconductor substrate. The method further includes forming insulating spacers on opposite sidewalls of the first trench and etching the semiconductor substrate below the first trench using the insulating spacers as an etch mask, to form a second trench below the first trench. In addition, the method includes filling the first and second trenches with an insulating material.Type: GrantFiled: September 11, 2020Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ta-Chun Lin, Tien-Shao Chuang, Kuang-Cheng Tai, Chun-Hung Chen, Chih-Hung Hsieh, Kuo-Hua Pan, Jhon-Jhy Liaw
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Patent number: 11195760Abstract: A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.Type: GrantFiled: March 19, 2020Date of Patent: December 7, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hung Chen, Chih-Hung Hsieh, Jhon-Jhy Liaw
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Publication number: 20210351038Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. The first gate electrode layer is in contact with a side wall of the separation plug.Type: ApplicationFiled: July 26, 2021Publication date: November 11, 2021Inventor: Chih-Hung HSIEH
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Patent number: 11164746Abstract: In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.Type: GrantFiled: June 26, 2018Date of Patent: November 2, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Hung Chen, Chih-Hung Hsieh, Jhon Jhy Liaw
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Patent number: 11075082Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. The first gate electrode layer is in contact with a side wall of the separation plug.Type: GrantFiled: December 17, 2018Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Chih-Hung Hsieh
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Publication number: 20210172246Abstract: An actuating system for a window shade includes a first rotary axle rotatable for displacing a bottom part, a second rotary axle rotatable for displacing an intermediate rail, and a limiting mechanism including a first and a second sliding part respectively linked movably to the first and second rotary axle. The first sliding part slides in a first direction when the first rotary axle rotates for lowering the bottom part and in a second direction when the first rotary axle rotates for raising the bottom part. The second sliding part slides in the first direction when the second rotary axle rotates for lowering the intermediate rail and in the second direction when the second rotary axle rotates for raising the intermediate rail. The first sliding part is prevented from sliding in the second direction via a contact between the first sliding part and the second sliding part.Type: ApplicationFiled: December 3, 2020Publication date: June 10, 2021Applicant: Teh Yor Co., Ltd.Inventors: Chung-Chen HUANG, Chih Hung HSIEH
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Publication number: 20210043635Abstract: A SRAM structure includes a first SRAM cell, a second SRAM cell arranged in mirror symmetry with the first SRAM cell along a first direction, a third SRAM cell arranged in mirror symmetry with the first SRAM cell along a second direction perpendicular to the first direction, and a fourth SRAM cell arranged in mirror symmetry with the third SRAM cell along the first direction and arranged in mirror symmetry with the second SRAM cell along the second direction. Each of SRAM cells includes a first and a second pull-down transistor. The SRAM structure further includes a contact bar extending in the second direction to sources of the second pull-down transistors of the first and third SRAM cells and extending in a third direction opposite to the second direction to sources of the second pull-down transistors of the second and fourth SRAM cells.Type: ApplicationFiled: October 26, 2020Publication date: February 11, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Hung HSIEH, Yu-Min LIAO, Jhon-Jhy LIAW
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Publication number: 20200411363Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first and second well regions with different conductivity types in a semiconductor substrate. A well interface is formed between the first and second well regions. The method also includes patterning the semiconductor substrate to form a first fin structure in the first well region, a second fin structure in the second well region, and a first trench between the first and second fin structures. The first trench exposes the well interface in the semiconductor substrate. The method further includes forming insulating spacers on opposite sidewalls of the first trench and etching the semiconductor substrate below the first trench using the insulating spacers as an etch mask, to form a second trench below the first trench. In addition, the method includes filling the first and second trenches with an insulating material.Type: ApplicationFiled: September 11, 2020Publication date: December 31, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ta-Chun LIN, Tien-Shao CHUANG, Kuang-Cheng TAI, Chun-Hung CHEN, Chih-Hung HSIEH, Kuo-Hua PAN, Jhon-Jhy LIAW
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Patent number: 10818675Abstract: SRAM structures are provided. A SRAM structure includes multiple SRAM cells arranged in multiple rows and multiple columns. A first SRAM cell is adjacent to a second SRAM cell in the same row. A third SRAM cell is adjacent to the first SRAM cell in the same column. A fourth SRAM cell is adjacent to the second SRAM in the same column. A contact plug is positioned between the first, second, third and fourth SRAM cells. A VSS line is electrically coupled to the first, second, third and fourth SRAM cells through the contact plug. The contact plug is free of the barrier layer.Type: GrantFiled: August 2, 2019Date of Patent: October 27, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hung Hsieh, Yu-Min Liao, Jhon-Jhy Liaw
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Patent number: 10790184Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region and a second well region that have different conductivity types and are adjacent to each other. A first fin structure protrudes from the semiconductor substrate and is formed in the first well region. A second fin structure protrudes from the semiconductor substrate and is formed in the second well region and adjacent to the first fin structure. A first multi-step isolation structure that includes a first isolation portion is formed between the first fin structure and the second fin structure. A second isolation portion extends from the bottom surface of the first isolation portion. The second isolation portion has a top width that is narrower than the bottom width of the first isolation portion.Type: GrantFiled: December 6, 2018Date of Patent: September 29, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ta-Chun Lin, Tien-Shao Chuang, Kuang-Cheng Tai, Chun-Hung Chen, Chih-Hung Hsieh, Kuo-Hua Pan, Jhon-Jhy Liaw
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Patent number: 10742668Abstract: A network attack pattern determination apparatus, method, and non-transitory computer readable storage medium thereof are provided. The apparatus is stored with several attack patterns and access records. Each access record includes a network address, time stamp, and access content. Each attack pattern corresponds to at least one attack access relation. Each attack access relation is defined by a network address and access content. The apparatus retrieves several attack records according to at least one attack address. The network address of each attack record is one of the attack address(s). The apparatus divides the attack records into several groups according to the time stamps and performs the following operations for each group: (a) creating at least one access relation for each attack address included in the group and (b) determining that the group corresponds to one of the attack patterns according to the at least one access relation of the group.Type: GrantFiled: December 7, 2016Date of Patent: August 11, 2020Assignee: Institute For Information IndustryInventors: Chia-Min Lai, Ching-Hao Mao, Chih-Hung Hsieh, Te-En Wei, Chi-Ping Lai
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Patent number: 10714488Abstract: A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns is formed over the dielectric structure. The contact-line-blocking patterns are formed using three or more lithography masks. A plurality of trenches is formed in the dielectric structure. The contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns. The trenches are filled with a conductive material to form a plurality of contact lines of the SRAM device.Type: GrantFiled: January 13, 2020Date of Patent: July 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Han Huang, Chih-Hung Hsieh
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Publication number: 20200219773Abstract: A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.Type: ApplicationFiled: March 19, 2020Publication date: July 9, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hung Chen, Chih-Hung Hsieh, Jhon-Jhy Liaw
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Patent number: 10685969Abstract: A read-only memory (ROM) structure is provided. The ROM device structure includes a first gate structure formed over a substrate, and the first gate structure includes a first work function layer with a first thickness. The ROM device structure includes an isolation structure formed over the substrate, and the isolation structure is adjacent to the first gate structure. The isolation structure includes a second work function layer with a second thickness, and the second thickness is larger than or smaller than the first thickness. The ROM device structure also includes a first contact structure formed over the substrate, and the first contact structure is between the first gate structure and the isolation structure.Type: GrantFiled: April 5, 2018Date of Patent: June 16, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Chih-Hung Hsieh
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Publication number: 20200152641Abstract: A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns is formed over the dielectric structure. The contact-line-blocking patterns are formed using three or more lithography masks. A plurality of trenches is formed in the dielectric structure. The contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns. The trenches are filled with a conductive material to form a plurality of contact lines of the SRAM device.Type: ApplicationFiled: January 13, 2020Publication date: May 14, 2020Inventors: Shih-Han Huang, Chih-Hung Hsieh
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Publication number: 20200135415Abstract: A switch module includes a switch base, a common terminal, a normally open terminal, a resilient piece, an upper cover and a soft element. The resilient piece includes a first portion and a second portion. The first portion of the resilient piece is disposed on the common terminal. The second portion of the resilient piece is located over the normally open terminal. The upper cover is disposed on the switch base to cover the common terminal, the normally open terminal and the resilient piece. The soft element is arranged between the upper cover and the second portion of the resilient piece. When an external force exerted on the resilient piece is eliminated, the second portion of the resilient piece is moved in a direction away from the switch base in response to an elastic restoring force of the resilient piece.Type: ApplicationFiled: December 26, 2018Publication date: April 30, 2020Inventors: Chia-Yuan Chang, Chun-Lin Chu, Chih-Hung Hsieh
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Patent number: 10629490Abstract: A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.Type: GrantFiled: October 1, 2018Date of Patent: April 21, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hung Chen, Chih-Hung Hsieh, Jhon-Jhy Liaw