Patents by Inventor Chih-Hung Lu

Chih-Hung Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250031404
    Abstract: A semiconductor device may include one or more transistor structures that include a plurality of source/drain regions and a gate structure between the source/drain regions. The semiconductor device may further include one or more dielectric layers between a source/drain contact structure and a gate structure of the one or more of the transistor structures. The one or more dielectric layers may be manufactured using on oxidation treatment process to tune the dielectric constant of the one or more dielectric layers. The dielectric constant of the one or more dielectric layers may be tuned to reduce the parasitic capacitance between the source/drain contact structure and the gate structure (which are conductive structures). In particular, the dielectric constant of the one or more spacer dielectric may be tuned using the oxidation treatment process to lower the as-deposited dielectric constant of the one or more dielectric layers.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 23, 2025
    Inventors: Min-Hsuan LU, Sheng-Tsung WANG, Huan-Chieh SU, Tzu Pei CHEN, Hao-Heng LIU, Chien-Hung LIN, Chih-Hao WANG
  • Publication number: 20250015011
    Abstract: The present disclosure provides a method for manufacturing a semiconductor device having a mark. The method includes: providing a substrate including a device region and a peripheral region adjacent to the device region; forming an interconnect layer over the substrate; depositing a first dielectric layer on the interconnect layer; forming a redistribution layer (RDL) over the first dielectric layer in the device region; depositing a second dielectric layer on the RDL in the device region and the first dielectric layer in the device region and the peripheral region; and removing portions of the second dielectric layer, the first dielectric layer and the interconnect structure in the peripheral region to form the mark in the peripheral region.
    Type: Application
    Filed: July 4, 2023
    Publication date: January 9, 2025
    Inventors: LIANG-SHIUAN PENG, CHIH-HUNG LU
  • Patent number: 12183697
    Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Yen-Ming Chen, Chih-Sheng Li, Hui-Chi Chen, Chih-Hung Lu, Dian-Hau Chen
  • Publication number: 20240363467
    Abstract: In order to reduce the incidence of stress concentration areas in an etched opening, a thinner polyimide layer is deposited to minimize gap formation therein, and a descum process is then performed to increase the angle of the presented layer surface. Reduction of the stress in this manner reduces the incidence of cracking of the later formed metal contact, which improves the overall pass rates of semiconductor devices so manufactured.
    Type: Application
    Filed: April 27, 2023
    Publication date: October 31, 2024
    Inventors: Jui-Wen SU, Shi-Hua TZENG, Chih-Hung LU, Po-Chi WU
  • Patent number: 12064179
    Abstract: A method for operating a near-eye display device is provided, which includes: disposing the near-eye display device in front of an eye of a user; forming a display image through the near-eye display device; changing the display image to perform a short-distance vision examination on the eye; changing the display image to perform a long-distance vision examination on the eye; obtaining vision examination data of the user according to results of the short-distance vision examination and the long-distance vision examination, and storing the vision examination data; and according to the vision examination data, adjusting a system parameter of the near-eye display device.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: August 20, 2024
    Assignee: Coretronic Corporation
    Inventors: Chih-Hung Lu, Chung-Jen Ou
  • Publication number: 20240274673
    Abstract: A HEMT device including a substrate structure, a channel layer, a barrier layer, a gate electrode, a drain electrode, a first source field plate, a second source field plate, and a dielectric structure is provided. The first source field plate extends from the second side of the gate electrode to the first side of the gate electrode. The second source field plate is located on the first side of the gate electrode and is located between the drain electrode and the first source field plate. There is a gap between the first source field plate and the second source field plate. The first source field plate has an end adjacent to the gap. The thickness of the dielectric structure located directly below the second source field plate is greater than the thickness of the dielectric structure located directly below the end of the first source field plate.
    Type: Application
    Filed: April 13, 2023
    Publication date: August 15, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Robin Christine Hwang, Jih-Wen Chou, Hwi-Huang Chen, Hsin-Hong Chen, Yu-Jen Huang, Chih-Hung Lu
  • Publication number: 20240170223
    Abstract: A method for manufacturing a semiconductor structure is provided. A first plate, a second plate, and a third plate are sequentially formed over a substrate. The first plate includes a first top surface, first sidewalls and first transition regions, wherein the first transition regions connect the first sidewalls to the first top surface. The second plate includes a second top surface, second sidewalls and second transition regions, wherein the second transition regions connect the second sidewalls to the second top surface, and the first transition regions are covered by the second plate. The third plate includes a third top surface, third sidewalls and third transition regions, wherein the third transition regions connect the third sidewalls to the third top surface, and the second transition regions are exposed by the third plate. A semiconductor structure thereof is also provided.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 23, 2024
    Inventors: LIANG-SHIUAN PENG, CHIH HUNG LU
  • Publication number: 20240145377
    Abstract: Some embodiments relate to an integrated chip including a first metal insulator metal (MIM) capacitor disposed over a substrate. The integrated chip further includes a second MIM capacitor disposed over the substrate. The first MIM capacitor has a first outer sidewall facing a second outer sidewall of the second MIM capacitor. A dielectric structure is arranged over and laterally between the first MIM capacitor and the second MIM capacitor. A base conductive layer is arranged between the first MIM capacitor and the second MIM capacitor and has a substantially flat upper surface. A metal core arranged on the substantially flat upper surface of the base conductive layer.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 2, 2024
    Inventors: Liang-Shiuan Peng, Chih-Hung Lu
  • Publication number: 20240079485
    Abstract: A high electron mobility transistor device including a channel layer, a first barrier layer, and a P-type gallium nitride layer is provided. The first barrier layer is disposed on the channel layer. The P-type gallium nitride layer is disposed on the first barrier layer. The first thickness of the first barrier layer located directly under the P-type gallium nitride layer is greater than the second thickness of the first barrier layer located on two sides of the P-type gallium nitride layer.
    Type: Application
    Filed: October 27, 2022
    Publication date: March 7, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Jih-Wen Chou, Chih-Hung Lu, Bo-An Tsai, Zheng-Chang Mu, Po-Hsien Yeh, Robin Christine Hwang
  • Patent number: 11914142
    Abstract: A method for generating virtual reality images and used in a light field near-eye display includes steps of: shifting a display image according to at least one change vector of a plurality of eye movement parameters, and calculating a compensation mask according to a simulated image and superimposing the compensation mask on a target image to generate a superimposed target image, wherein brightness distributions of the simulated image and the compensation mask are opposite to each other. The light field near-eye display is also provided. In this way, the light field near-eye display for generating virtual reality images and the method thereof can achieve the purpose of improving the uniformity of the image and expanding the eye box size.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: February 27, 2024
    Assignee: Coretronic Corporation
    Inventors: Chih-Hung Lu, Jui-Yi Wu
  • Publication number: 20240030081
    Abstract: A semiconductor assembly includes a semiconductor device and a seal ring. The seal ring is disposed adjacent to the semiconductor device. The seal ring includes a first side surface inclined from a top surface of the seal ring toward a bottom surface of the seal ring, wherein a lateral width of the bottom surface of the seal ring is larger than a lateral width of the top surface of the seal ring; and a first metal line disposed in the seal ring and comprising a second side surface adjacent to the first side surface of the seal ring. A maximum distance between the second side surface of the first metal line and the first side surface of the seal ring is in a range of 5 ?m to 30 ?m.
    Type: Application
    Filed: July 20, 2022
    Publication date: January 25, 2024
    Inventors: LIANG-SHIUAN PENG, CHIH-HUNG LU
  • Publication number: 20240019983
    Abstract: A capacitive hover sensing module includes: a capacitive touch panel for sensing a self-capacitive projective position of a conductor object on the capacitive touch panel; a touch driver chip drives the capacitive touch panel for measuring a sensing signal induced by the conductor object, and generates and outputs a sensing data accordingly; a processor receives the sensing data output and thereby generates the self-capacitive projective position of the conductor object on the capacitive touch panel when the conductor object hovers over the capacitive touch panel, the processor also generates a hover value related to a vertical distance between the conductor object and the capacitive touch panel, wherein the capacitive hover sensing module transmits the self-capacitive projective position and the hover value to a display device to display the self-capacitive projective position of the conductor object on the capacitive touch panel through a corresponding positioning feedback icon.
    Type: Application
    Filed: August 8, 2022
    Publication date: January 18, 2024
    Applicant: EMERGING DISPLAY TECHNOLOGIES CORP.
    Inventor: Chih-Hung LU
  • Publication number: 20240014037
    Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing a semiconductor structure. The semiconductor structure includes a first set of photoresist structures, a second photoresist structure, and a third photoresist structure. The first set of photoresist structures is disposed along a first orientation. The second photoresist structure is disposed non-parallel to the first orientation. The third photoresist structure is disposed non-parallel to the first orientation. The second photoresist structure and the third photoresist structure contact at least one of the first set of photoresist structures.
    Type: Application
    Filed: July 7, 2022
    Publication date: January 11, 2024
    Inventors: LIANG-SHIUAN PENG, CHIH-HUNG LU
  • Publication number: 20230411279
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes an interconnect structure disposed over a substrate, a first conductive feature disposed in the interconnect structure, a dielectric layer disposed on the interconnect structure, and a second conductive feature having a top portion and a bottom portion. The top portion is disposed over the dielectric layer, and the bottom portion is disposed through the dielectric layer. The structure further includes an adhesion layer disposed over the dielectric layer and the second conductive feature. The adhesion layer includes a first portion disposed on a top of the second conductive feature and a second portion disposed over the dielectric layer, the first portion has a thickness, and the second portion has a width substantially greater than the thickness.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 21, 2023
    Inventors: Liang-Hsuan PENG, Chih-Hung LU, Chih-Lin WANG, Song-Bor LEE
  • Patent number: 11842662
    Abstract: A light field near-eye display device and a light field near-eye display method are provided. The light field near-eye display device includes a processor, a display panel, and a lens module. The processor calculates new ray tracing data based on a current eye relief, preset eye relief data, and preset ray tracing data, and adjusts preset image data according to the new ray tracing data to generate adjusted image data. The display panel is coupled to the processor and emits an image beam according to the adjusted image data. The lens module includes a microlens array and is disposed between the display panel and a pupil. The image beam is incident to the pupil through the lens module and displays a light field image.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: December 12, 2023
    Assignee: Coretronic Corporation
    Inventors: Jui-Yi Wu, Chih Hung Lu
  • Patent number: 11841513
    Abstract: A light field near-eye display device and a method of light field near-eye display are provided. The light field near-eye display device includes a processor, a display panel, and a lens module. The processor adjusts a preset eye box according to a vision data to obtain an adjusted eye box, and adjusts a preset image data according to the adjusted eye box to generate an adjusted image data. The display panel is coupled to the processor and emits an image beam according to the adjusted image data. The lens module includes a micro lens array and is disposed between the display panel and a pupil. The image beam is incident on the pupil via the lens module and displays a light field image.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: December 12, 2023
    Assignee: Coretronic Corporation
    Inventors: Jui-Yi Wu, Chih-Hung Lu
  • Publication number: 20230329545
    Abstract: A method for operating a near-eye display device is provided, which includes: disposing the near-eye display device in front of an eye of a user; forming a display image through the near-eye display device; changing the display image to perform a short-distance vision examination on the eye; changing the display image to perform a long-distance vision examination on the eye; obtaining vision examination data of the user according to results of the short-distance vision examination and the long-distance vision examination, and storing the vision examination data; and according to the vision examination data, adjusting a system parameter of the near-eye display device.
    Type: Application
    Filed: April 12, 2023
    Publication date: October 19, 2023
    Applicant: Coretronic Corporation
    Inventors: Chih-Hung Lu, Chung-Jen Ou
  • Publication number: 20230317651
    Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 5, 2023
    Inventors: Chih-Fan Huang, Yen-Ming Chen, Chih-Sheng Li, Hui-Chi Chen, Chih-Hung Lu, Dian-Hau Chen
  • Publication number: 20230299169
    Abstract: A high electron mobility transistor device including a channel layer, a first barrier layer, a gate structure, and a spacer is provided. The first barrier layer is disposed on the channel layer. The gate structure is disposed on the first barrier layer. The gate structure includes a first P-type gallium nitride layer, a second barrier layer, and a second P-type gallium nitride layer. The first P-type gallium nitride layer is disposed on the first barrier layer. The second barrier layer is disposed on the first P-type gallium nitride layer. The second P-type gallium nitride layer is disposed on the second barrier layer. A width of the second P-type gallium nitride layer is smaller than a width of the first P-type gallium nitride layer. The spacer is disposed on a sidewall of the second P-type gallium nitride layer.
    Type: Application
    Filed: September 12, 2022
    Publication date: September 21, 2023
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Jih-Wen Chou, Hsin-Hong Chen, Yu-Jen Huang, Robin Christine Hwang, Po-Hsien Yeh, Chih-Hung Lu
  • Publication number: 20230209039
    Abstract: A control method of a light field display is provided. A control unit inputs a focal length signal to a zoom lens, so that the zoom lens is periodically switched among corresponding specific focal lengths. The control unit inputs a corresponding display signal to a display unit of a display module according to one of the specific focal lengths, and the display module generates one of image lights, the image lights respectively have different imaging distances corresponding to the specific focal lengths after passing through the zoom lens. The control unit inputs a corresponding response time signal to the display module according to one of the specific focal lengths, the one of image lights emitted by the display module passes through the zoom lens within one of response times, and the light field display projects the one of image lights to form an image at the corresponding imaging distance.
    Type: Application
    Filed: December 7, 2022
    Publication date: June 29, 2023
    Applicant: Coretronic Corporation
    Inventors: Chih-Hung Lu, Chung-Jen Ou