Abstract: Disclosed are a testing device and a testing method thereof. The testing device includes a frame, a flexible multi-layer substrate and at least one electrical testing point. The frame is positioned corresponding to a chip. At least one electrical connecting point is formed on a surface of the chip. The flexible multi-layer substrate is fixed in the frame. The electrical testing point is corresponding to the electrical connecting point and formed on an upper surface of the flexible multi-layer substrate for contacting the electrical connecting point and performing an electrical test to the chip. Furthermore, the electrical connecting point or the electrical testing point is a bump.

Abstract: Disclosed is a chip thermal dissipation structure, employed in an electronic device comprising a first chip having a first chip face and a first chip back, comprising chip molding material, covering a lateral of the first chip; a first case, contacting the first chip back; a packaging substrate, connecting with the first chip face via first bumps; and a print circuit board, having a first surface and a second surface and connecting with the packaging substrate via solders. The chip thermal dissipation structure further comprises a second case, contacting the second surface. The thermal energy generated by the first chip is conducted toward the first case via the first chip back and toward the second case via the first chip face, the first bumps, the packaging substrate, the solders and the print circuit board.

Abstract: Disclosed is a chip thermal dissipation structure, employed in an electronic device comprising a first chip having a first chip face and a first chip back, comprising chip molding material, covering a lateral of the first chip; a first case, contacting the first chip back; a packaging substrate, connecting with the first chip face via first bumps; and a print circuit board, having a first surface and a second surface and connecting with the packaging substrate via solders. The chip thermal dissipation structure further comprises a second case, contacting the second surface. The thermal energy generated by the first chip is conducted toward the first case via the first chip back and toward the second case via the first chip face, the first bumps, the packaging substrate, the solders and the print circuit board.

Abstract: Disclosed is a via structure in a multi-layer substrate, comprising a first metal layer, a dielectric layer and a second metal layer. The first metal layer has an upper surface. The dielectric layer covers the first metal layer in which a via is opened to expose the upper surface. The second metal layer is formed in the via and contacts an upper surface and an inclined wall of the via. A contacting surface of the second metal layer has a top line lower than the upper edge of the inclined wall. Alternatively, the second metal layer can be formed on the dielectric layer as being a metal line simultaneously as formed in the via as being a pad. The metal line and the pad are connected electronically. The aforesaid metal second layer can be formed in the via and on the dielectric layer by a metal lift-off process.

Abstract: The present invention provides a time adjusting method and system for a time piece (such as a wristwatch), which utilizes a motion sensor disposed on the wristwatch to detect a hand gesture made by a user in the front of the wristwatch. In such a manner, adjusting the position of an indicator on the wristwatch is realized, and thereby carrying out the time adjustment.

Abstract: The present invention provides a wristwatch structure, an electronic crown for wristwatch, and a wristwatch having a display. The wristwatch structure comprises an electric driving component; an electronic core having a plurality of two-dimensional joints; and an electronic crown comprising a rotating portion and a fixed detecting portion, the detecting portion detecting electronic signals according to a rotation of the rotating portion; wherein the detecting portion of the electronic crown exports the electronic signals to the electronic core via one of the joints, and the electric driving component is electrically connected to one set of joints among the two-dimensional joints. The present invention can improve compatibility for various designs, thereby shortening product development cycle. Also, the present invention is suitable for developing a product with appearance similar to a mechanical watch.

Abstract: The present invention provides a wristwatch structure, an electronic core for a wristwatch, and a method for manufacturing the wristwatch. The wristwatch structure comprises: a dial; an indicator designed with the dial; an electric driving component connected to the indicator, for driving the indicator and actuating it; and an electronic core having an integrated circuit unit packaged therein, the electronic core also having a plurality of two-dimensional joints distributed on an external surface thereof, wherein the electric driving component is electrically connected to the integrated circuit unit of the electronic core via one set of joints among the two-dimensional joints. The present invention can improve compatibility for various designs, thereby shortening the product development cycle.

Abstract: Disclosed is a core module, comprising: a package substrate, having a plurality of pads; a first component, connected to the pads of the package substrate corresponding to the first component with a plurality of first joint parts; a second component, connected to the pads of the package substrate corresponding to the first component with a plurality of second joint parts; and a third component, connected to the pads of the package substrate corresponding to the third component with a plurality of third joint parts, wherein the first component is positioned above the second component relative to the lower package substrate, and the first component, the second component and the third component are all electrically connected via the package substrate, and a main molding material is molding the first component, the second component and the third component.

Abstract: Disclosed is a manufacturing method of metal structure in multi-layer substrate. The manufacturing method includes following steps: coating at least one photoresist layer on a surface of a dielectric layer; exposing the photoresist dielectric layer to define a predetermined position of the metal structure; removing the photoresist layer at the predetermined position to undercut an edge of the photoresist layer adjacent to the predetermined position by a horizontal distance of at least 0.1 ?m between a top and a bottom of the edge; forming the metal structure at the predetermined position; and forming at least one top-cover metal layer to cover a top surface and two side surfaces of the metal structure. The present invention can form a cover metal layer covering the top surface and the two side surfaces by one single photomask.

Abstract: Disclosed are a package structure and a package method. The package structure comprises an IC bare die, having bare die pads formed on a surface; a flexible packaging substrate, having first pads formed on a first surface and second pads formed on a second surface; and a plurality of bumps, previously formed on the first surface of the flexible packaging substrate. The bumps have different heights, and correspond to the first pads and contact the bare die pads respectively. Pressing or heating is implemented to package the IC bare die. The package structure further comprises a printed circuit board, having a plurality of contact pads. The second pads of the flexible packaging substrate respectively contact with the contact pads via solders. Connection is implemented by pressing or heating. Extremely low stress is generated to the packaging substrate and the printed circuit board.

Abstract: Disclosed are a testing device and a testing method thereof. The testing device includes a frame, a flexible multi-layer substrate and at least one electrical testing point. The frame is positioned corresponding to a chip. At least one electrical connecting point is formed on a surface of the chip. The flexible multi-layer substrate is fixed in the frame. The electrical testing point is corresponding to the electrical connecting point and formed on an upper surface of the flexible multi-layer substrate for contacting the electrical connecting point and performing an electrical test to the chip. Furthermore, the electrical connecting point or the electrical testing point is a bump.

Abstract: Disclosed is a chip thermal dissipation structure, employed in an electronic device comprising a first chip having a first chip face and a first chip back, comprising chip molding material, covering a lateral of the first chip; a first case, contacting the first chip back; a packaging substrate, connecting with the first chip face via first bumps; and a print circuit board, having a first surface and a second surface and connecting with the packaging substrate via solders. The chip thermal dissipation structure further comprises a second case, contacting the second surface. The thermal energy generated by the first chip is conducted toward the first case via the first chip back and toward the second case via the first chip face, the first bumps, the packaging substrate, the solders and the print circuit board.

Abstract: Disclosed is a multi-layer via structure, comprising a metal layer, a first via metal layer formed on a first open of a first dielectric layer and a second via metal layer formed on a second open of a second dielectric layer. The first and second via metal layers comprise first and second bottoms, first and second top portions, first and second inclined walls, respectively. The first and second inclined walls comprise first and second top edges, first and second bottom edges respectively. The second top edge has a point closest to a geometric center of the first bottom. A vertical projection of the point falls on the first inclined wall. Alternatively, a point of the second bottom edge, which is closest to the geometric center, has a vertical projection. The vertical projection is vertical to the metal layer and falls on the first inclined wall.

Abstract: Disclosed is a metal structure of a multi-layer substrate, comprising a first metal layer and a dielectric layer. The first metal layer has an embedded base and a main body positioned on the embedded base. The base area of the embedded base is larger than the base area of the main body. After the dielectric layer covers the main body and the embedded base, the dielectric layer is opened at the specific position of the first metal layer for connecting the first metal layer with a second metal layer above the dielectric layer. When the metal structure is employed as a pad or a metal line of the flexible multi-layer substrate according to the present invention, the metal structure cannot easily be delaminated or separated from the contacted dielectric layer. Therefore, a higher reliability for the flexible multi-layer substrate can be achieved.

Abstract: Disclosed is a metal structure of a multi-layer substrate, comprising a first metal layer and a dielectric layer. The first metal layer has an embedded base and a main body positioned on the embedded base. The base area of the embedded base is larger than the base area of the main body. After the dielectric layer covers the main body and the embedded base, the dielectric layer is opened at the specific position of the first metal layer for connecting the first metal layer with a second metal layer above the dielectric layer. When the metal structure is employed as a pad or a metal line of the flexible multi-layer substrate according to the present invention, the metal structure cannot easily be delaminated or separated from the contacted dielectric layer. Therefore, a higher reliability for the flexible multi-layer substrate can be achieved. A manufacturing method thereof is also provided.

Abstract: A surface finish structure of multi-layer substrate and manufacturing method thereof. The surface finish structure of the present invention includes a bond pad layer, at least one cover metal layer and a solder mask. The cover metal layer covers the bond pad layer. The solder mask has a hole to expose the cover metal layer. The present invention can form the cover metal layer to cover the bond pad layer and then forms the solder mask. Thereafter, the hole is made to the solder mask at the position of the cover metal layer to expose thereof. Because the bond pad layer is embedded in a dielectric layer of the multi-layer substrate, adhesion intensity between the bond pad layer and the dielectric layer can be enhanced. Meanwhile, contact of the bond pad layer with the solder can be prevented with the cover metal layer.

Abstract: The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The IC integrated substrate has a first dielectric layer attached to the carrier. The materials of the carrier and the first dielectric layer are selected to prevent the IC integrated substrate from peeling off the carrier during processing and to allow the IC integrated substrate to naturally separate from the carrier after being cut, through the adhesion between the carrier and the first dielectric layer. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electrical devices using the above structure.

Abstract: Disclosed are a multi-layer substrate and a manufacturing method of the multi-layer substrate. By employing a carrier to alternately form dielectric layers and metal structure layers thereon. Each dielectric layer adheres with the adjacent dielectric layer to embed the metal structure layers in the dielectric layers corresponding thereto. Comparing with prior arts, which have to use prepregs when hot pressing and adhering different layers of different materials, the present invention takes fewer processes, thus, fewer kinds of materials without using prepregs. Therefore, the present invention can promote the entire quality and yield of manufacturing the multi-layer substrate to satisfy mechanical characteristic matching of the multi-layer substrate and to reduce cost of the whole manufacturing process.

Abstract: Disclosed are a multi-layer substrate and a manufacturing method of the multi-layer substrate. By employing a carrier to alternately form dielectric layers and metal structure layers thereon. Each dielectric layer adheres with the adjacent dielectric layer to embed the metal structure layers in the dielectric layers corresponding thereto. Comparing with prior arts, which have to use prepregs when hot pressing and adhering different layers of different materials, the present invention takes fewer processes, thus, fewer kinds of materials without using prepregs. Therefore, the present invention can promote the entire quality and yield of manufacturing the multi-layer substrate to satisfy mechanical characteristic matching of the multi-layer substrate and to reduce cost of the whole manufacturing process.

Abstract: Disclosed is a manufacturing method of metal structure in multi-layer substrate. The manufacturing method includes following steps: coating at least one photoresist layer on a surface of a dielectric layer; exposing the photoresist dielectric layer to define a predetermined position of the metal structure; removing the photoresist layer at the predetermined position to undercut an edge of the photoresist layer adjacent to the predetermined position by a horizontal distance of at least 0.1 ?m between a top and a bottom of the edge; forming the metal structure at the predetermined position; and forming at least one top-cover metal layer to cover a top surface and two side surfaces of the metal structure. The present invention can form a cover metal layer covering the top surface and the two side surfaces by one single photomask.