Patents by Inventor Chih-Min Liu

Chih-Min Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210103655
    Abstract: A security monitoring apparatus and method for a vehicle network are provided. The apparatus transmits an indicator and an encryption key to a plurality of electronic control units via the controller area network interface. The apparatus receives a response code from each electronic control unit via the controller area network interface, wherein each of the response codes is generated by a serial number of each electronic control unit and the encryption key via a hash algorithm. The apparatus compares the response code returned by each electronic control unit according to a list, the encryption key and the hash algorithm to determine whether each electronic control unit correctly returns the response code. The apparatus determines to generate an alert signal when one of the electronic control units does not correctly return the response code.
    Type: Application
    Filed: November 25, 2019
    Publication date: April 8, 2021
    Inventors: I-Chou HUNG, Chih-Min SHIH, Hsing-Yu CHEN, Wen-Kai LIU
  • Publication number: 20210091047
    Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Inventors: Meng-Tse Chen, Chung-Shi Liu, Chih-Wei Lin, Hui-Min Huang, Hsuan-Ting Kuo, Ming-Da Cheng
  • Publication number: 20210066091
    Abstract: A four signal line unit cell is formed on a substrate using a combination of an extreme ultraviolet photolithography process and one or more self aligned deposition processes. The photolithography process and the self aligned deposition processes result in spacers on a hard mask above the substrate. The spacers define a pattern of signal lines to be formed on the substrate for a unit cell. The photolithography process and self aligned deposition processes result in signal lines having a critical dimension much smaller than features that can be defined by the extreme ultraviolet photolithography process.
    Type: Application
    Filed: June 5, 2020
    Publication date: March 4, 2021
    Inventors: Chih-Min HSIAO, Chien-Wen LAI, Ru-Gun LIU, Chih-Ming LAI, Wei-Shuo SU, Yu-Chen CHANG
  • Publication number: 20210014447
    Abstract: A circuit is disclosed, including a sensing unit and first to fifth switching units. The sensing unit generates a sensing voltage to a sensing node. The first switching unit is coupled between the sensing node and a first node. The second switching unit is coupled between the sensing node and a second node and generates a first auxiliary voltage to the second node. The first capacitive unit is coupled to the second node. The third switching unit is coupled between the first and second nodes, and adjusts a first transfer voltage at the first node. The fourth switching unit is coupled between the sensing node and a third node, and generates a second transfer voltage to the third node. The fifth switching unit is coupled between the sensing node and a fourth node and generates a second auxiliary voltage to the fourth node.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chih-Min LIU
  • Patent number: 10879907
    Abstract: One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PPL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Chih-Min Liu
  • Patent number: 10879306
    Abstract: A micro semiconductor structure is provided. The micro semiconductor structure includes a substrate, a plurality of micro semiconductor devices disposed on the substrate, and a first supporting layer disposed between the substrate and the micro semiconductor devices. Each of the micro semiconductor devices has a first electrode and a second electrode disposed on a lower surface of the micro semiconductor devices. The lower surface includes a region, wherein the region is between the first electrode and the second electrode. An orthographic projection of the first supporting layer on the substrate at least overlaps an orthographic projection of a portion of the region on the substrate. The first supporting layer directly contacts the region.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: December 29, 2020
    Assignee: PLAYNITRIDE DISPLAY CO., LTD.
    Inventors: Chih-Ling Wu, Ying-Tsang Liu, Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Yu-Chu Li, Huan-Pu Chang, Yu-Yun Lo, Yi-Min Su, Tzu-Yang Lin, Yu-Hung Lai
  • Publication number: 20200403077
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Patent number: 10868994
    Abstract: An image sensor system includes a timing control circuit, an image sensor and a modulation circuit. The timing control circuit is arranged to determine if a coding condition is fit according to an input signal and generate a control signal when the coding condition is fit. The input signal has a signal value updated in response to each pulse of a clock signal. The image sensor is coupled to the timing control circuit, and includes a plurality of pixels. One of the plurality of pixels receives the control signal from the timing control circuit and outputs a sensing signal. The modulation circuit is coupled to the image sensor, and arranged to receive the sensing signal and generate an output signal according to the sensing signal.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chih-Min Liu
  • Patent number: 10861827
    Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chung-Shi Liu, Chih-Wei Lin, Hui-Min Huang, Hsuan-Ting Kuo, Ming-Da Cheng
  • Publication number: 20200361894
    Abstract: The present invention provides novel substituted benzimidazole derivatives used as DAAO inhibitors and for treatment and/or prevention of neurological disorders.
    Type: Application
    Filed: September 14, 2017
    Publication date: November 19, 2020
    Inventors: Yufeng Jane TSENG, Yu-Li LIU, Chung-Ming SUN, Wen-Sung LAI, Chih-Min LIU, Hai-Gwo HWU
  • Publication number: 20200350197
    Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.
    Type: Application
    Filed: July 21, 2020
    Publication date: November 5, 2020
    Inventors: Chih-Wei Lin, Hui-Min Huang, Ai-Tee Ang, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20200338796
    Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Feng Weng, Ching-Hua Hsieh, Chung-Shi Liu, Chih-Wei Lin, Sheng-Hsiang Chiu, Yao-Tong Lai, Chia-Min Lin
  • Publication number: 20200336673
    Abstract: Methods and systems for capturing a three dimensional image are described. An image capture process is performed while moving a lens to capture image data across a range of focal depths, and a three dimensional image reconstruction process generates a three dimensional image based on the image data. A two-dimensional image is also rendered including focused image data from across the range of focal depths. The two dimensional image and the three dimensional image are fused to generate a focused three dimensional model.
    Type: Application
    Filed: July 1, 2020
    Publication date: October 22, 2020
    Inventor: Chih-Min Liu
  • Patent number: 10804365
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: October 13, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Patent number: 10798328
    Abstract: A circuit includes sensing unit, first and second group of switches, capacitor, and readout circuit. The sensing unit is configured to receive light and generate sensing voltage at sensing node in response to the light. The first group of switches is coupled to the sensing node, and configured to generate first transfer voltage to first node and generate first auxiliary voltage to second node. The second group of switches is coupled to the sensing node, and configured to generate second transfer voltage to third node and generate second auxiliary voltage to fourth node. The capacitor is coupled to the first group of switches, and configured to store charges generated from the sensing unit. The readout circuit is configured to read at least one of the first transfer voltage and the first auxiliary voltage, and read at least one of the second transfer voltage and the second auxiliary voltage.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chih-Min Liu
  • Publication number: 20200243370
    Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Inventors: Chih-Wei Lin, Hui-Min Huang, Ai-Tee Ang, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20200227264
    Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Patent number: 10715718
    Abstract: Methods and systems for capturing a three dimensional image are described. An image capture process is performed while moving a lens to capture image data across a range of focal depths, and a three dimensional image reconstruction process generates a three dimensional image based on the image data. A two-dimensional image is also rendered including focused image data from across the range of focal depths. The two dimensional image and the three dimensional image are fused to generate a focused three dimensional model.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chih-Min Liu
  • Publication number: 20200176508
    Abstract: A micro semiconductor structure is provided. The micro semiconductor structure includes a substrate, a plurality of micro semiconductor devices disposed on the substrate, and a first supporting layer disposed between the substrate and the micro semiconductor devices. Each of the micro semiconductor devices has a first electrode and a second electrode disposed on a lower surface of the micro semiconductor devices. The lower surface includes a region, wherein the region is between the first electrode and the second electrode. An orthographic projection of the first supporting layer on the substrate at least overlaps an orthographic projection of a portion of the region on the substrate. The first supporting layer directly contacts the region.
    Type: Application
    Filed: June 7, 2019
    Publication date: June 4, 2020
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Chih-Ling WU, Ying-Tsang LIU, Pei-Hsin CHEN, Yi-Chun SHIH, Yi-Ching CHEN, Yu-Chu LI, Huan-Pu CHANG, Yu-Yun LO, Yi-Min SU, Tzu-Yang LIN, Yu-Hung LAI
  • Publication number: 20200176267
    Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.
    Type: Application
    Filed: November 19, 2019
    Publication date: June 4, 2020
    Inventors: Chih-Min HSIAO, Chih-Ming LAI, Chien-Wen LAI, Ya Hui CHANG, Ru-Gun LIU