Patents by Inventor Chih-Min Liu

Chih-Min Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7639592
    Abstract: A system of sampling interface for an optical pick-up head comprises an optical pick-up head, a PMOS, a boost circuit, and a sample and hold circuit. The optical pick-up head outputs one of a reading voltage and a writing voltage. The PMOS gate receives the gate voltage and then the PMOS is turned on to pass the reading voltage to the sample and hold circuit. Moreover, the substrate of the PMOS receives a control voltage. The boost circuit is used to boost the gate voltage higher than the control voltage for turning off the PMOS and isolating the writing voltage.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: December 29, 2009
    Inventor: Chih-Min Liu
  • Publication number: 20090309550
    Abstract: An auto-rechargeable wireless computer peripheral includes a wireless power supply module and a wireless receiving module. The wireless power supply module is used for transmitting an electromagnetic wave. The wireless receiving module is corresponding to the wireless power supply module, for receiving the electromagnetic wave, converting the electromagnetic wave into an electric power, and storing the electric power. When the electric power stored by the wireless receiving module is lower than a rated value, the wireless receiving module outputs a charging signal, and the wireless power supply module receives the charging signal and transmits the electromagnetic wave in response to the charging signal, so as to automatically charge the wireless receiving module.
    Type: Application
    Filed: August 14, 2008
    Publication date: December 17, 2009
    Applicant: KYE SYSTEMS CORP.
    Inventor: Chih-Min Liu
  • Patent number: 7536574
    Abstract: The present invention relates to a wireless computer peripheral device that comprises a first power detecting unit with a set first threshold value, coupled to the first power and; and a second power detecting unit with a set second threshold value, coupled to the first power, second power and the first power detecting unit; thereby, the power energy supplied from the second power will be cut off and the power energy supplied from the first power will be provided to the wireless computer peripheral device for using when the power energy stored in the first power is higher than the power energy stored in the second power; and the power energy supplied from the first power will be cut off and the power energy supplied from the second power will be provided to the wireless computer peripheral device for using when the power energy stored in the first power is lower than or equal to the power energy stored in the second power.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: May 19, 2009
    Assignee: Kye Systems Corporation
    Inventor: Chih-Min Liu
  • Publication number: 20080315276
    Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.
    Type: Application
    Filed: July 21, 2008
    Publication date: December 25, 2008
    Inventor: Chih-Min Liu
  • Publication number: 20080315275
    Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.
    Type: Application
    Filed: July 21, 2008
    Publication date: December 25, 2008
    Inventor: Chih-Min Liu
  • Patent number: 7466172
    Abstract: Supply voltage level detectors are disclosed. The supply voltage level detector comprises a voltage source divider dividing a voltage source to generate a detection voltage, a bandgap reference voltage generator, a comparator comparing the detection voltage with a bandgap reference voltage generated by the bandgap reference voltage generator to determine if the voltage source is ready, a control circuit, and a forcing circuit. To ensure reliability of the comparison result, the control circuit disables the comparing device until the bandgap reference voltage is available. The forcing circuit is coupled to the output terminal of the comparing device and is controlled by the control circuit. When the comparing device is disabled, the forcing circuit forces the voltage level of the output terminal of the comparing device to a specific value indicating the voltage source is unready.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: December 16, 2008
    Assignee: Via Technologies, Inc.
    Inventor: Chih-Min Liu
  • Patent number: 7443211
    Abstract: Transmitter and transmission circuit. For realizing a differential transmitter, a switch circuit is connected between two load transistors of two complementary MOS pairs. The switch circuit can have two inductors. When the two complementary MOS pairs are conducting current to drive signal transition at output nodes, the inductors open to make the load transistors stop draining current. Also, the switch circuit can have switch transistor controlled by an edge detector for detecting raising and falling edges of the input signals, such that the switch circuit can make the load transistors stop draining current accordingly. In this way, raising and falling edges of the output signals are emphasized to improve signal propagation.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: October 28, 2008
    Assignee: VIA Technologies Inc.
    Inventor: Chih-Min Liu
  • Patent number: 7417275
    Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: August 26, 2008
    Assignee: VIA Technologies, Inc.
    Inventor: Chih-Min Liu
  • Publication number: 20080054843
    Abstract: A linear battery chargers is disclosed which comprises a current generator, a current detector, an operational amplifier, and a multiplexing device. The current generator provides current to charge a battery module, and the current is detected and transformed to a detected voltage by the current detector. The operational amplifier has an output terminal coupled to a control terminal of the current generator. In a constant current charge mode, the multiplexing device couples a first reference voltage and the detected voltage to first and second input terminals of the operational amplifier, respectively. The current generated by the current generator is maintained at a constant current level. In a constant voltage charge mode, the multiplexing device couples a second reference voltage and the voltage level of the battery module to the first and second input terminals of the operational amplifier, respectively. The voltage level of the battery module gradually approaches a constant voltage level.
    Type: Application
    Filed: June 6, 2007
    Publication date: March 6, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Chih-Min Liu
  • Publication number: 20080054996
    Abstract: Supply voltage level detectors are disclosed. The supply voltage level detector comprises a voltage source divider dividing a voltage source to generate a detection voltage, a bandgap reference voltage generator, a comparator comparing the detection voltage with a bandgap reference voltage generated by the bandgap reference voltage generator to determine if the voltage source is ready, a control circuit, and a forcing circuit. To ensure reliability of the comparison result, the control circuit disables the comparing device until the bandgap reference voltage is available. The forcing circuit is coupled to the output terminal of the comparing device and is controlled by the control circuit. When the comparing device is disabled, the forcing circuit forces the voltage level of the output terminal of the comparing device to a specific value indicating the voltage source is unready.
    Type: Application
    Filed: June 6, 2007
    Publication date: March 6, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Chih-Min Liu
  • Patent number: 7263054
    Abstract: A sample-and-hold interface circuit of a pickup head uses a circuit switch to control a voltage divider. When the circuit switch receives a signal Break, a voltage divider does not consume extra power to decrease the driving power consumption of a pickup head. And a controller can sample an unattenuated input signal to increase the signal/noise ratio.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: August 28, 2007
    Assignee: Via Technologies Inc.
    Inventor: Chih-Min Liu
  • Publication number: 20070152749
    Abstract: A transmission circuit and related method are disclosed. A transmitter in the transmission circuit has CMOS transistors as driving units for responding an input signal to drive an output signal at an output node, and each driving unit has a corresponding charge unit formed by a capacitor-connected MOS of a same type as that of the corresponding driving unit. Each charge unit is controlled by an auxiliary signal inverse to the input signal. When a level transition occurs in the input signal, the charge unit can compensate charge injection and clock feed-through caused by the driving unit at the output node, and form peaks for pre-emphasis. In this way, a better transmission property can be realized by using a simpler and low-power circuit design.
    Type: Application
    Filed: October 3, 2006
    Publication date: July 5, 2007
    Inventor: Chih-Min Liu
  • Publication number: 20070139086
    Abstract: Transmitter and transmission circuit. For realizing a differential transmitter, a switch circuit is connected between two load transistors of two complementary MOS pairs. The switch circuit can have two inductors. When the two complementary MOS pairs are conducting current to drive signal transition at output nodes, the inductors open to make the load transistors stop draining current. Also, the switch circuit can have switch transistor controlled by an edge detector for detecting raising and falling edges of the input signals, such that the switch circuit can make the load transistors stop draining current accordingly. In this way, raising and falling edges of the output signals are emphasized to improve signal propagation.
    Type: Application
    Filed: November 22, 2006
    Publication date: June 21, 2007
    Inventor: Chih-Min Liu
  • Publication number: 20070135066
    Abstract: The present invention relates to a wireless computer peripheral device that comprises a first power detecting unit with a set first threshold value, coupled to the first power and; and a second power detecting unit with a set second threshold value, coupled to the first power, second power and the first power detecting unit; thereby, the power energy supplied from the second power will be cut off and the power energy supplied from the first power will be provided to the wireless computer peripheral device for using when the power energy stored in the first power is higher than the power energy stored in the second power; and the power energy supplied from the first power will be cut off and the power energy supplied from the second power will be provided to the wireless computer peripheral device for using when the power energy stored in the first power is lower than or equal to the power energy stored in the second power.
    Type: Application
    Filed: March 17, 2006
    Publication date: June 14, 2007
    Inventor: Chih-Min Liu
  • Patent number: 7215160
    Abstract: A switched operation amplifier including a biased circuit, an amplifier circuit, and a buffer circuit is provided. The biased circuit is to provide a first, a second, and a third biased signals by means of an input signal and a reference current source. The amplifier circuit is driven by the biased signals through current mirrors, a sample-and-hold switch, a complementary sample-and-hold switch and a differential pair. The buffer circuit includes a capacitor and two transistors in series. An output signal is generated from a node in between the two transistors, and fed back to a negative terminal of the differential pair of the amplifier circuit. The amplifier circuit charges the capacitor and controls one of the transistors of the buffer circuit until the voltages of a positive and the negative terminal of the differential pair are equal. By means of the operation of the switched op amplifier, the output voltage can be kept being stable.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: May 8, 2007
    Assignee: Via Technologies, Inc.
    Inventor: Chih-Min Liu
  • Patent number: 7095263
    Abstract: The present invention provides one hysteresis circuit device. The hysteresis circuit device includes an input voltage level generator, a switch, and a comparator. The input voltage level generator is used to receive an input signal and output a high input voltage and a low threshold voltage. The switch is used to receive the high input voltage and the low threshold voltage, and output a switch output signal according to a digital signal. The comparator has one terminal used to receive the switch output signal, and another terminal used to receive a reference signal. Then, the comparator outputs the digital signal. The hysteresis circuit device can change their voltage levels by an external circuit; therefore, the noise resulting from the input signal can be avoided and the problem of false detection of the comparator can be solved.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: August 22, 2006
    Assignee: VIA Technologies, Inc.
    Inventor: Chih-Min Liu
  • Publication number: 20060066360
    Abstract: A switched operation amplifier including a biased circuit, an amplifier circuit, and a buffer circuit is provided. The biased circuit is to provide a first, a second, and a third biased signals by means of an input signal and a reference current source. The amplifier circuit is driven by the biased signals through current mirrors, a sample-and-hold switch, a complementary sample-and-hold switch and a differential pair. The buffer circuit includes a capacitor and two transistors in series. An output signal is generated from a node in between the two transistors, and fed back to a negative terminal of the differential pair of the amplifier circuit. The amplifier circuit charges the capacitor and controls one of the transistors of the buffer circuit until the voltages of a positive and the negative terminal of the differential pair are equal. By means of the operation of the switched op amplifier, the output voltage can be kept being stable.
    Type: Application
    Filed: September 28, 2005
    Publication date: March 30, 2006
    Inventor: Chih-Min Liu
  • Publication number: 20060002282
    Abstract: A system of sampling interface for an optical pick-up head comprises an optical pick-up head, a PMOS, a boost circuit, and a sample and hold circuit. The optical pick-up head outputs one of a reading voltage and a writing voltage. The PMOS gate receives the gate voltage and then the PMOS is turned on to pass the reading voltage to the sample and hold circuit. Moreover, the substrate of the PMOS receives a control voltage. The boost circuit is used to boost the gate voltage higher than the control voltage for turning off the PMOS and isolating the writing voltage.
    Type: Application
    Filed: March 25, 2005
    Publication date: January 5, 2006
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Chih-Min Liu
  • Publication number: 20050281168
    Abstract: A system of sampling interface for an optical pick-up head includes an optical pick-up head, a switch circuit and a sample and hold circuit. The optical pick-up head outputs one of a reading voltage and a writing voltage. The switch circuit includes a NMOS. The NMOS has a first source/drain for receiving the reading voltage and the writing voltage, and has a gate for receiving the gate voltage. The NMOS turns on the first source/drain and the second source/drain when receiving the reading voltage, and turns them off when receiving the writing voltage. Finally, a sample and hold circuit connects to the second source/drain of the NMOS for sampling and holding the reading voltage.
    Type: Application
    Filed: March 28, 2005
    Publication date: December 22, 2005
    Inventor: Chih-Min Liu
  • Publication number: 20050213475
    Abstract: A sample-and-hold interface circuit of a pickup head uses a circuit switch to control a voltage divider. When the circuit switch receives a signal Break, a voltage divider does not consume extra power to decrease the driving power consumption of a pickup head. And a controller can sample an unattenuated input signal to increase the signal/noise ratio.
    Type: Application
    Filed: August 27, 2004
    Publication date: September 29, 2005
    Inventor: Chih-Min Liu