Abstract: One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PPL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.

Abstract: A circuit includes a voltage controlled oscillator (“VCO”) having a VCO cell. The VCO cell includes a first transistor and a second transistor. The first transistor has a gate terminal coupled to a first node that also is coupled to a low-pass filter from which the gate terminal receives a first control voltage signal. A second terminal of the first transistor is connected to a first voltage source. The second transistor has a gate terminal coupled to a second node that is disposed between a capacitor and a resistor of the low pass filter. The second transistor has a second terminal connected to the first voltage source. The second transistor is larger than the first transistor, and the VCO has an output terminal for providing an output frequency signal.

Abstract: A circuit includes a sensing unit, a first group of switching units, and a second group of switching units. The sensing unit is configured to receive light and generate a sensing voltage at a sensing node in response to the light. The first group of switching units is coupled to the sensing node, and configured to generate a first transfer voltage to a first node and generate a first auxiliary voltage to a second node. At least one of the first transfer voltage and the first auxiliary voltage is read by a readout circuit. The second group of switching units is coupled to the sensing node, and configured to generate a second transfer voltage to a third node and generate a second auxiliary voltage to a fourth node. At least one of the second transfer voltage and the second auxiliary voltage is read by the readout circuit.

Abstract: A sensor includes a plurality of image sensors, wherein each image sensor of the plurality of image sensors is configured to detect a first spectrum of light. The sensor further includes a depth sensing pixel bonded to each image sensor of the plurality of image sensors, wherein the depth sensing pixel is configured to detect a second spectrum of light different from the first spectrum.

Abstract: One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PLL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.

Abstract: The invention utilizes virtual screening strategy to seek for current market drugs as anti-schizophrenia therapy drug repurposing. Drug repurposing strategy finds new uses other than the original medical indications of existing drugs. Finding new indications for such drugs will benefit patients who are in needs for a potential new therapy sooner since known drugs are usually with acceptable safety and pharmacokinetic profiles. In this study, repurposing marketed drugs for DAAO inhibitor as new schizophrenia therapy was performed with virtual screening on marketed drugs and its metabolites. The identified and available drugs and compounds were further confirmed with in vitro DAAO enzymatic inhibitory assay.

Abstract: A method of making a composite pixel image sensor includes forming an image sensing array; and forming a depth sensing pixel. The depth sensing pixel includes a depth sensing photodiode; a first photo storage diode; and a first transistor configured to selectively couple the depth sensing photodiode to the first photo storage diode. The depth sensing pixel further includes a second photo storage diode different from the first photo storage device; and a second transistor configured to selectively couple the depth sensing photodiode to the second photo storage device. The depth sensing pixel further includes a first transfer gate configured to selectively couple the first photo storage diode to a first output node. The depth sensing pixel further includes a second transfer gate configured to selectively couple the second photo storage diode to a second output node. The method includes bonding the image sensing array to the depth sensing pixel.

Abstract: A phase-locked loop (PLL) circuit is disclosed. The PLL circuit includes a detecting circuit configured to detect a phase difference between a digitally controlled oscillator (DCO) clock signal and a reference clock signal, and generate a difference signal based on the detected phase difference; a digitized difference generator, coupled to the detecting circuit, configured to generate a control code based upon the difference signal; and a DCO configured to generate the DCO output signal responsive to the control code of the digitized difference generator; wherein the detecting circuit, the digitized difference generator and the DCO form a closed loop and reduce the phase difference between the DCO output signal and the reference clock signal. An associated method and a circuit are also disclosed.

Abstract: A sensing device includes: a sampling circuit arranged to sample a sensing signal for generating a signal in response to a sampling signal having a monotonically increasing waveform; and a conversion circuit arranged to convert the signal into a digital output signal when the signal reaches a predetermined threshold of the conversion circuit.

Abstract: A method of making a composite pixel image sensor includes forming an image sensing array; and forming a depth sensing pixel. The depth sensing pixel includes a depth sensing photodiode; a first photo storage diode; and a first transistor configured to selectively couple the depth sensing photodiode to the first photo storage diode. The depth sensing pixel further includes a second photo storage diode different from the first photo storage device; and a second transistor configured to selectively couple the depth sensing photodiode to the second photo storage device. The depth sensing pixel further includes a first transfer gate configured to selectively couple the first photo storage diode to a first output node. The depth sensing pixel further includes a second transfer gate configured to selectively couple the second photo storage diode to a second output node. The method includes bonding the image sensing array to the depth sensing pixel.

Abstract: A phase-locked loop (PLL) circuit is disclosed. The PLL circuit includes a detecting circuit configured to detect a phase difference between a digitally controlled oscillator (DCO) clock signal and a reference clock signal, and generate a difference signal based on the detected phase difference; a digitized difference generator, coupled to the detecting circuit, configured to generate a control code based upon the difference signal; and a DCO configured to generate the DCO output signal responsive to the control code of the digitized difference generator; wherein the detecting circuit, the digitized difference generator and the DCO form a closed loop and reduce the phase difference between the DCO output signal and the reference clock signal. An associated method and a circuit are also disclosed.

Abstract: A depth sensing pixel includes a photodiode; a first photo storage device; and a first transistor configured to selectively couple the photodiode to the first photo storage device. The depth sensing pixel further includes a second photo storage diode different from the first photo storage device; and a second transistor configured to selectively couple the photodiode to the second photo storage device. The depth sensing pixel further includes a first transfer gate configured to selectively couple the first photo storage diode to a first output node. The depth sensing pixel further includes a second transfer gate configured to selectively couple the second photo storage diode to a second output node.

Abstract: A depth sensing pixel includes a photodiode; a first photo storage device; and a first transistor configured to selectively couple the photodiode to the first photo storage device. The depth sensing pixel further includes a second photo storage diode different from the first photo storage device; and a second transistor configured to selectively couple the photodiode to the second photo storage device. The depth sensing pixel further includes a first transfer gate configured to selectively couple the first photo storage diode to a first output node. The depth sensing pixel further includes a second transfer gate configured to selectively couple the second photo storage diode to a second output node.

Abstract: A Dual-Side Illumination (DSI) image sensor chip includes a first image sensor chip configured to sense light from a first direction, and a second image sensor chip aligned to, and bonded to, the first image sensor chip. The second image sensor chip is configured to sense light from a second direction opposite the first direction.

Abstract: An active capacitive stylus and a sensing method thereof are provided. The active capacitive stylus includes a pen tip, a frequency adjuster, a frequency generating module, and a control module. The pen tip includes a contact component for moving in response to a pressing force. The frequency adjuster simultaneously moves with the contact component. The frequency generating module generates an induction frequency according to an induction distance between the frequency adjuster and the frequency generating module. The control module is electrically connected to the frequency generating module and calculates a pressure value according to the induction frequency.

Abstract: A Dual-Side Illumination (DSI) image sensor chip includes a first image sensor chip configured to sense light from a first direction, and a second image sensor chip aligned to, and bonded to, the first image sensor chip. The second image sensor chip is configured to sense light from a second direction opposite the first direction.

Abstract: One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PPL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.

Abstract: A circuit includes a voltage controlled oscillator (“VCO”) having a VCO cell. The VCO cell includes a first transistor and a second transistor. The first transistor has a gate terminal coupled to a first node that also is coupled to a low-pass filter from which the gate terminal receives a first control voltage signal. A second terminal of the first transistor is connected to a first voltage source. The second transistor has a gate terminal coupled to a second node that is disposed between a capacitor and a resistor of the low pass filter. The second transistor has a second terminal connected to the first voltage source. The second transistor is larger than the first transistor, and the VCO has an output terminal for providing an output frequency signal.

Abstract: A system is disclosed for a voltage controlled oscillator (“VCO”) having a large frequency range and a low gain. Passive or active circuitry is introduced between at least one VCO cell in the voltage controlled oscillator and the voltage source for the VCO cell which reduces a gain value for the VCO to maintain stability of the system.

Abstract: A system and method is disclosed for reducing inter symbol interference in a high speed data transfer system. One or more decision logic circuits and one or more pull circuits are used to enable the signal level of a bit in a serial bit stream to achieve its nominal value.