Chih-Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.
Abstract: A pipelined analog-to-digital converter includes: a first switched capacitor network, a first digital-to-analog converter, a second switched capacitor network, a second digital-to-analog converter, and an operational amplifier. The outputs from the first switched capacitor network and the first digital-to-analog converter form a first subtraction signal. The outputs from the second switched capacitor network and the second digital-to-analog converter form a second subtraction signal. The operational amplifier is arranged to operably generate an output signal based on the first subtraction signal or the second subtraction signal, and to operably switch coupling relationship of multiple candidate capacitors of the operational amplifier based on the magnitude of an input signal of a prior stage circuit, so that only a portion of the multiple candidate capacitors could be participated in the generation of the output signal at a time.
October 12, 2018
Date of Patent:
January 14, 2020
REALTEK SEMICONDUCTOR CORP.
Chih-Lung Chen, Shih-Hsiung Huang, Chien-Ming Wu, Jie-Fan Lai
Abstract: An operational amplifier includes: a first gain stage for generating a second signal based on a first signal transmitted from a prior stage circuit; a second gain stage for generating an output signal based on the second signal; multiple candidate capacitors; and a capacitor selection circuit for switching the coupling relationship of the multiple candidate capacitors based on the magnitude of an input signal of the prior stage circuit, so that only a portion of the multiple candidate capacitors could be coupled to the second gain stage at a time.
Abstract: A semiconductor structure includes a first transistor including a first gate structure over a first active region in a substrate, a second transistor including a second gate structure over a second active region in the substrate, and a butted contact electrically connecting the second active region of the second transistor to the first gate structure of the first transistor. The butted contact includes a first portion extending along a first direction and overlapping at least the second active region, and a second portion extending along a second direction different from the first direction and intersecting the first portion. The second portion extends over the first gate structure.
April 26, 2019
January 2, 2020
You Che CHUANG, Chih-Ming LEE, Hsin-Chi CHEN, Hsun-Ying HUANG
Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.
Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.
Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.
Abstract: A 3D printing device including a base, a gantry, a forming platform, a tank, an adjustable platform, a driving module and a control module is provided. The gantry and the tank are respectively disposed on the base. The forming platform is movably assembled to the gantry. The adjusting platform is disposed between the gantry and the forming platform or between the tank and the base. The driving module is connected to the forming platform and the gantry. The control module is electrically connected to the driving module to drive the forming platform to reciprocate along the gantry, so that the forming platform is moved into or out of the tank. Before 3D printing is performed, the control module moves the forming platform to lean against the tank through the driving module, so as to drive the adjustable platform to deform, and confirm consistency of contact surfaces of the forming platform and the tank.
August 31, 2018
December 19, 2019
XYZprinting, Inc., Kinpo Electronics, Inc.
Abstract: A tool calibration apparatus includes a first measuring device, a second measuring device, a third measuring device, a fourth measuring device and a fifth measuring device. The first measuring device includes a first measuring surface, a first measuring edge and a sensor. The second measuring device includes a second measuring surface, a second measuring edge and a sensor. The third measuring device includes a third measuring edge and a sensor. The fourth measuring device includes a fourth measuring edge and a sensor. The fifth measuring device includes a third measuring surface and a sensor. The first measuring surface, the first measuring edge and the third measuring edge are movable in an X-axis direction. The second measuring surface, the second measuring edge and the fourth measuring edge are movable in a Y-axis direction. The third measuring surface is movable in a Z-axis direction.
Abstract: A resin composition is provided. The resin composition comprises the following constituents: (A) epoxy resin; (B) a compound of formula (I), in formula (I), R1 and R2 are independently —H, —CH3, or —C(CH3); and (C) an optional filler.
Abstract: A method and apparatus for loop filter processing of video data in a video encoder or decoder are disclosed. Embodiments according to the present invention conditionally allow sharing of loop filter parameters. In one embodiment, sharing of loop filter information between the current block and a neighboring block is determined according to a condition. If the condition indicates that sharing of loop filter information is allowed, a merge flag is coded and incorporated in the video bitstream in an encoder, and a merge flag is parsed from the video bitstream and decoded in a decoder. In one embodiment, the condition depends on region partitioning of the picture, where region partitioning partitions the picture into regions and the region may correspond to a slice or a tile. The condition is set to indicate that sharing of loop filter information is allowed if the block and the neighboring block are in a same slice/tile.
Abstract: A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiCxN(2-x), and x is in a range of 0.1 to 0.9; and filling a reflective material in the trench and over the corrosion resistive layer.
Abstract: A formation tank includes a tank body and a release film. The tank body includes a bottom plate and a tank wall. One face of the bottom plate is an inner bottom surface, and at least one engagement structure is formed on the inner bottom surface. The tank wall protrudes from the inner bottom surface and surrounds a periphery of the bottom plate. The release film is attached on the inner bottom surface and the release film is mortise-and-tenon connected to the engagement structure. An engagement structure is arranged on the bottom plate to improve an engagement force between the bottom plate and the release film. Accordingly, the release film is prevented from being detached, and therefore durability of the release film is also improved.
Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.
Abstract: The present disclosure is generally related to semiconductor devices, and more particularly to a dielectric material formed in semiconductor devices. The present disclosure provides methods for forming a dielectric material layer by a cyclic spin-on coating process. In an embodiment, a method of forming a dielectric material on a substrate includes spin-coating a first portion of a dielectric material on a substrate, curing the first portion of the dielectric material on the substrate, spin-coating a second portion of the dielectric material on the substrate, and thermal annealing the dielectric material to form an annealed dielectric material on the substrate.
May 30, 2018
December 5, 2019
Je-Ming Kuo, Yen-Chun Huang, Chih-Tang Peng, Tien-I Bao
Abstract: A method for manufacturing a semiconductor includes following steps. An epitaxial structure including a first semiconductor material and a second semiconductor material is provided. A lattice constant of the second semiconductor material is greater than a lattice constant of the first semiconductor material. A metal-containing layer is deposited on the epitaxial structure. The metal containing layer includes a first metal material and a second metal material. An atomic size of the second metal material is greater than an atomic size of the first metal material. The metal-containing layer and the epitaxial structure are annealed to form a metal silicide layer on the epitaxial structure. The metal silicide layer includes the first semiconductor material, the second semiconductor material, the first metal material, and the second metal material.
January 26, 2018
Date of Patent:
November 19, 2019
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.
Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
Abstract: A method of using a polishing system includes securing a wafer to a support, wherein the wafer has a first diameter. The method further includes polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter. The method further includes rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad. The method further includes polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter. The method further includes releasing the wafer from the support following polishing the wafer using the second polishing pad.
Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, a bottom electrode layer, a first dielectric layer, a top electrode layer and first dielectric spacers. The bottom electrode layer is positioned over the substrate. The first dielectric layer is positioned over the bottom electrode layer. The top electrode layer is positioned over the first dielectric layer. The first dielectric spacers are positioned on opposite sidewalls of the bottom electrode layer. The first dielectric layer has a first dielectric constant. The first dielectric spacers have a second dielectric constant that is lower than the first dielectric constant.