Patents by Inventor Chih-Ming Huang
Chih-Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8866236Abstract: A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect.Type: GrantFiled: April 29, 2010Date of Patent: October 21, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chi-Hsin Chiu, Chih-Ming Huang, Chang-Yueh Chan, Hsin-Yi Liao, Chun-Chi Ke
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Patent number: 8802507Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.Type: GrantFiled: November 2, 2012Date of Patent: August 12, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Cheng-Chia Chiang, Chin-Huang Chang, Chien-Ping Huang, Chih-Ming Huang, Jung-Pin Huang
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Patent number: 8716070Abstract: A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process.Type: GrantFiled: March 15, 2013Date of Patent: May 6, 2014Assignee: Siliconware Precision Industries Co. Ltd.Inventors: Chi-Hsin Chiu, Chih-Ming Huang, Chang-Yueh Chan, Hsin-Yi Liao, Chun-Chi Ke
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Publication number: 20140080264Abstract: A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier s greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.Type: ApplicationFiled: November 21, 2013Publication date: March 20, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTDInventors: Chang-Yueh Chan, Chih-Ming Huang, Chun-Yuan Li, Chih-Hsin Lai
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Patent number: 8618641Abstract: A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier is greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.Type: GrantFiled: August 11, 2008Date of Patent: December 31, 2013Assignee: Siliconware Precision Industries Co., LtdInventors: Chang-Yueh Chan, Chih-Ming Huang, Chun-Yuan Li, Chih-Hsin Lai
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Patent number: 8564115Abstract: Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.Type: GrantFiled: June 8, 2012Date of Patent: October 22, 2013Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chang-Yueh Chan, Chien-Ping Huang, Chun-Chi Ke, Chun-An Huang, Chih-Ming Huang
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Patent number: 8546183Abstract: A heat dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted on a chip carrier. A heat sink is mounted on the chip, and includes an insulating core layer, a thin metallic layer formed on each of an upper surface and a lower surface of the insulating core layer and a thermal via hole formed in the insulating core layer. A molding process is performed to encapsulate the chip and the heat sink with an encapsulant to form a package unit. A singulation process is performed to peripherally cut the package unit. A part of the encapsulant above the thin metallic layer on the upper surface of the heat sink is removed, such that the thin metallic layer on the upper surface of the heat sink is exposed, and heat generated by the chip can be dissipated through the heat sink.Type: GrantFiled: September 30, 2008Date of Patent: October 1, 2013Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Ping Huang, Chih-Ming Huang
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Patent number: 8420430Abstract: A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process.Type: GrantFiled: April 28, 2010Date of Patent: April 16, 2013Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chi-Hsin Chiu, Chih-Ming Huang, Chang-Yueh Chan, Hsin-Yi Liao, Chun-Chi Ke
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Patent number: 8367926Abstract: An electronic apparatus includes an enclosure defining a connector port, and a cover mechanism. The cover mechanism includes a bracket mounted to the enclosure, a cover rotatably mounted to the bracket to cover or uncover the connector port. The cover includes an elastic lock. When the cover is rotated to cover the connector port, the elastic lock is engaged with a sidewall of the connector port.Type: GrantFiled: November 11, 2010Date of Patent: February 5, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Wen-Tang Peng, Chih-Ming Huang
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Patent number: 8304891Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.Type: GrantFiled: December 4, 2008Date of Patent: November 6, 2012Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Cheng-Chia Chiang, Chin-Huang Chang, Chien-Ping Huang, Chih-Ming Huang, Jung-Pin Huang
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Publication number: 20120241937Abstract: Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.Type: ApplicationFiled: June 8, 2012Publication date: September 27, 2012Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chang-Yueh Chan, Chien-Ping Huang, Chun-Chi Ke, Chun-An Huang, Chih-Ming Huang
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Patent number: 8241059Abstract: A connector and printed circuit board assembly includes a printed circuit board, a connector fixed on the printed circuit board, and a fixing board fixed on the connector, the fixing board defining a through hole, a connecting member fixed on the printed circuit board adjacent to the connector, a threaded retainer, and a threaded post securely connected with the connecting member. The threaded post passes through the through hole and seats the threaded retainer to lock the connector onto the printed circuit board.Type: GrantFiled: June 3, 2010Date of Patent: August 14, 2012Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Wei-Chao Huang, Chih-Ming Huang
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Patent number: 8198689Abstract: Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.Type: GrantFiled: April 28, 2010Date of Patent: June 12, 2012Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chang-Yueh Chan, Chien-Ping Huang, Chun-Chi Ke, Chun-An Huang, Chih-Ming Huang
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Patent number: 8183092Abstract: A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.Type: GrantFiled: July 2, 2010Date of Patent: May 22, 2012Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Ping Huang, Chih-Ming Huang, Han-Ping Pu, Yu-Po Wang, Cheng-Hsu Hsiao
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Publication number: 20120108088Abstract: An electronic apparatus includes an enclosure defining a connector port, and a cover mechanism. The cover mechanism includes a bracket mounted to the enclosure, a cover rotatably mounted to the bracket to cover or uncover the connector port. The cover includes an elastic lock. When the cover is rotated to cover the connector port, the elastic lock is engaged with a sidewall of the connector port.Type: ApplicationFiled: November 11, 2010Publication date: May 3, 2012Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: WEN-TANG PENG, CHIH-MING HUANG
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Publication number: 20110237121Abstract: A connector and printed circuit board assembly includes a printed circuit board, a connector fixed on the printed circuit board, and a fixing board fixed on the connector, the fixing board defining a through hole, a connecting member fixed on the printed circuit board adjacent to the connector, a threaded retainer, and a threaded post securely connected with the connecting member. The threaded post passes through the through hole and seats the threaded retainer to lock the connector onto the printed circuit board.Type: ApplicationFiled: June 3, 2010Publication date: September 29, 2011Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: WEI-CHAO HUANG, CHIH-MING HUANG
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Patent number: 8013443Abstract: An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings for exposing the bond pads. A groove is formed between the paired bond pads and has a length larger than a width of an electronic component mounted on the paired bond pads. The groove is adjacent to one of the paired bond pads and communicates with a corresponding one of the openings where this bond pad is exposed. Accordingly, a clearance between the electronic component and the electronic carrier board can be effectively filled with an insulating resin for encapsulating the electronic component, thereby preventing voids and undesirable electrical bridging between the paired bond pads from occurrence.Type: GrantFiled: March 19, 2010Date of Patent: September 6, 2011Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Fang-Lin Tsai, Ho-Yi Tsai, Chih-Ming Huang, Chien-Ping Huang
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Publication number: 20110177643Abstract: A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process.Type: ApplicationFiled: April 28, 2010Publication date: July 21, 2011Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chi-Hsin Chiu, Chih-Ming Huang, Chang-Yueh Chan, Hsin-Yi Liao, Chun-Chi Ke
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Publication number: 20110175179Abstract: A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect.Type: ApplicationFiled: April 29, 2010Publication date: July 21, 2011Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chi-Hsin Chiu, Chih-Ming Huang, Chang-Yueh Chan, Hsin-Yi Liao, Chun-Chi Ke
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Patent number: D711383Type: GrantFiled: January 9, 2014Date of Patent: August 19, 2014Assignees: Tongfang Global Limited, Shengyang Tongfang Multimedia Technology Co., Ltd.Inventors: Th Lam, Wen-Sheng Lu, Chih-Ming Huang, Tsung-Hsien Chuang, Christopher Ng