Patents by Inventor Chih-Ming Kuo

Chih-Ming Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8841767
    Abstract: A bumping process comprises steps of forming a metal layer with copper on a substrate, and the metal layer with copper comprises a plurality of first zones and second zones; forming a photoresist layer on the metal layer with copper; patterning the photoresist layer to form a plurality of openings; forming a plurality of copper bumps within the openings, each of the copper bumps covers the first zones and comprises a first top surface; forming a connection layer on the first top surface; removing the photoresist layer; removing the second zones and enabling each of the first zones to form an under bump metallurgy layer, wherein the under bump metallurgy layer, the copper bump, and the connection layer possess their corresponded peripheral walls, and covering sections of a first protective layer formed on the connection layer may cover those peripheral walls to prevent ionization phenomenon.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: September 23, 2014
    Assignee: Chipbond Technology Corporation
    Inventors: Chin-Tang Hsieh, Chih-Ming Kuo
  • Patent number: 8823169
    Abstract: A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: September 2, 2014
    Assignee: Chipbond Technology Corporation
    Inventors: Chih-Ming Kuo, Lung-Hua Ho, Shih-Chieh Chang, Chia-Yeh Huang, Chin-Tang Hsieh
  • Publication number: 20140217578
    Abstract: A semiconductor package process includes the following steps, providing a first substrate having a first metal bump, the first metal bump comprises a joint portion having a first softening point; providing a second substrate having a second metal bump having a top surface, a lateral surface and a second softening point, wherein the first softening point is smaller than the second softening point; performing a heating procedure to make the joint portion of the first metal bump become a softened state; and laminating the first substrate on the second substrate to make the second metal bump embedded into the joint portion in the softened state to make the top surface and the lateral surface of the at least one second metal bump being clad extendedly by compressing the joint portion in the softened state.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 7, 2014
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Lung-Hua Ho, Fei-Jain Wu, Chih-Ming Kuo, Shih-Chieh Chang, Chia-Jung Tu
  • Patent number: 8772644
    Abstract: A carrier with three-dimensional capacitor includes a substrate and a three-dimensional capacitor, wherein the substrate comprises a trace layer having a first terminal and a second terminal. The three-dimensional capacitor is integrally formed as one piece with the trace layer. The three-dimensional capacitor and the trace layer are made of same material. The three-dimensional capacitor comprises a first capacitance portion and a second capacitance portion, the first capacitance portion comprises a first section, a second section and a first passage, the second capacitance portion is formed at the first passage. The second capacitance portion comprises a third section, a fourth section and a second passage communicated with the first passage. The first capacitance portion is located at the second passage, a first end of the first capacitance portion connects to the first terminal, and a third end of the second capacitance portion connects to the second terminal.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: July 8, 2014
    Assignee: Chipbond Technology Corporation
    Inventors: Chih-Ming Kuo, Lung-Hua Ho, You-Ming Hsu
  • Publication number: 20140141606
    Abstract: A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.
    Type: Application
    Filed: January 27, 2014
    Publication date: May 22, 2014
    Applicant: Chipbond Technology Corporation
    Inventors: Chih-Ming Kuo, Lung-Hua Ho, Shih-Chieh Chang, Chia-Yeh Huang, Chin-Tang Hsieh
  • Publication number: 20140117540
    Abstract: A semiconductor manufacturing method includes providing a substrate having a metallic layer that includes a first metal layer and a second metal layer, the first metal layer comprises plural base areas and plural first outer lateral areas, the second metal layer comprises plural second base areas and plural second outer lateral areas; forming a first photoresist layer; forming plural bearing portions; removing the first photoresist layer; forming a second photoresist layer; forming plural connection portions, each connection portion comprises a first connection layer and a second connection layer; removing the second photoresist layer to reveal the connection portions and the bearing portions; removing the first outer lateral areas; reflowing the second connection layers to form plural composite bumps; removing the second outer lateral areas to make the first base areas and the second base areas form plural under bump metallurgy layers.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chih-Ming Kuo, Lung-Hua Ho, Kung-An Lin, Sheng-Hui Chen
  • Publication number: 20140120715
    Abstract: A semiconductor manufacturing method includes providing a carrier having a metallic layer, wherein the metallic layer comprises a plurality of base areas and a plurality of outer lateral areas; forming a first photoresist layer; forming a plurality of bearing portions; removing the first photoresist layer to reveal the bearing portions, each bearing portion comprises a bearing surface having a first area and a second area; forming a second photoresist layer for revealing the first areas of the bearing surfaces; forming a plurality of connection portions, wherein the first areas of the bearing surfaces are covered by the connection portions to make each connection portion connect with each bearing portion to form a snap bump; removing the outer lateral areas of the metallic layer to make the base areas form a plurality of under bump metallurgy layers.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chih-Ming Kuo, Lung-Hua Ho, Kung-An Lin, Sheng-Hui Chen
  • Patent number: 8704345
    Abstract: A semiconductor package includes a lead frame, at least one chip and a molding compound. The lead frame comprises a plurality of leads, each lead comprises a first end portion and at least one coupling protrusion, wherein the first end portion comprises a first upper surface, the coupling protrusion comprises a ring surface and is integrally formed as one piece with the first upper surface. The chip disposed on top of the leads comprises a plurality of bumps and a plurality of solders, the coupling protrusions embed into the solders to make the ring surfaces of the coupling protrusions cladded with the solders. The solders cover the first upper surfaces. The chip and the leads are cladded with the molding compound.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: April 22, 2014
    Assignee: Chipbond Technology Corporation
    Inventors: Chih-Ming Kuo, Shih-Chieh Chang, Chih-Hsien Ni, Chin-Tang Hsieh, Chia-Jung Tu, Lung-Hua Ho
  • Patent number: 8692390
    Abstract: A pyramid bump structure for electrically coupling to a bond pad on a carrier comprises a conductive block disposed at the bond pad and an oblique pyramid insulation layer covered at one side of the conductive block. The oblique pyramid insulation layer comprises a bottom portion and a top portion, and outer diameter of the oblique pyramid insulation layer is tapered from the bottom portion to the top portion. When the carrier is connected with a substrate and an anisotropic conductive film disposed at the substrate, the pyramid bump structure may rapidly embed into the anisotropic conductive film to raise the flow rate of the anisotropic conductive film. Further, a short phenomenon between adjacent bumps can be avoided to raise the yield rate of package process.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: April 8, 2014
    Assignee: Chipbond Technology Corporation
    Inventors: Chih-Hung Wu, Lung-Hua Ho, Chih-Ming Kuo, Cheng-Hung Shih, Yie-Chuan Chiu
  • Patent number: 8658528
    Abstract: A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: February 25, 2014
    Assignee: Chipbond Technology Corporation
    Inventors: Chih-Ming Kuo, Yie-Chuan Chiu, Lung-Hua Ho
  • Patent number: 8658466
    Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: February 25, 2014
    Assignee: Chipbond Technology Corporation
    Inventors: Chin-Tang Hsieh, Chih-Ming Kuo, Chia-Jung Tu, Shih-Chieh Chang, Chih-Hsien Ni, Lung-Hua Ho, Chaun-Yu Wu, Kung-An Lin
  • Publication number: 20140035125
    Abstract: A semiconductor manufacturing method includes providing a carrier having a metallic layer, wherein the metallic layer comprises a plurality of base areas and a plurality of outer lateral areas; forming a first photoresist layer; forming a plurality of bearing portions; removing the first photoresist layer to reveal the bearing portions, each bearing portion comprises a bearing surface having a first area and a second area; forming a second photoresist layer for revealing the first areas of the bearing surfaces; forming a plurality of connection portions, wherein the first areas of the bearing surfaces are covered by the connection portions to make each connection portion connect with each bearing portion to form a snap bump; removing the outer lateral areas of the metallic layer to make the base areas form a plurality of under bump metallurgy layers.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chih-Ming Kuo, Lung-Hua Ho, Kung-An Lin, Sheng-Hiu Chen
  • Publication number: 20140035126
    Abstract: A semiconductor manufacturing method includes providing a substrate having a metallic layer that includes a first metal layer and a second metal layer, the first metal layer comprises plural base areas and plural first outer lateral areas, the second metal layer comprises plural second base areas and plural second outer lateral areas; forming a first photoresist layer; forming plural bearing portions; removing the first photoresist layer; forming a second photoresist layer; forming plural connection portions, each connection portion comprises a first connection layer and a second connection layer; removing the second photoresist layer to reveal the connection portions and the bearing portions; removing the first outer lateral areas; reflowing the second connection layers to form plural composite bumps; removing the second outer lateral areas to make the first base areas and the second base areas form plural under bump metallurgy layers.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chih-Ming Kuo, Lung-Hua Ho, Kung-An Lin, Sheng-Hiu Chen
  • Publication number: 20140027905
    Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.
    Type: Application
    Filed: October 1, 2013
    Publication date: January 30, 2014
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chin-Tang Hsieh, Chih-Ming Kuo, Chia-Jung Tu, Shih-Chieh Chang, Chih-Hsien Ni, Lung-Hua Ho, Chaun-Yu Wu, Kung-An Lin
  • Publication number: 20140021601
    Abstract: A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.
    Type: Application
    Filed: October 4, 2012
    Publication date: January 23, 2014
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chih-Ming Kuo, Lung-Hua Ho, Shih-Chieh Chang, Chia-Yeh Huang, Chin-Tang Hsieh
  • Patent number: 8633744
    Abstract: A power reset circuit with zero standby current consumption includes a power storage unit, first, second, and third voltage detection units, a switching unit, and a power reset unit. The power storage unit stores electric power by a supply voltage source. The first, second, and third voltage detection units are connected to the supply voltage source to start a switching circuit of the first, second, and third voltage detection units in accordance with a change in a normal supply stage, a shutdown stage, and a voltage ramp-up stage of the supply voltage source, control a voltage level of the power reset unit, and thereby generate the power reset signal. Accordingly, the power reset circuit does not consume current in a standby state (the normal supply stage of the supply voltage source) and thus is characterized by zero current consumption.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: January 21, 2014
    Assignee: Eon Silicon Solutions, Inc.
    Inventors: Hsiao-Hua Lu, Chih-Ming Kuo, Yu-Chun Wang
  • Publication number: 20140010013
    Abstract: A memory erasing method and a driving circuit thereof are introduced, when cells are selected to be erased, the method includes setting gates of cells which are not selected to be erased and are located at a selected block, drains of all the cells in a selected bank, and the gate of the unselected cells to be floating; supplying a positive voltage to all the sources in a selected bank and their shared P well and N well; and supplying a negative voltage to the gates of the cells located in a selected block and selected to be erased. Accordingly, a positive coupling voltage from P wells is received whenever gates are floating, so as to inhibit erasure of unselected blocks and thereby streamline decoding, thus making it easy to attain further expansion of blocks or banks with a small layout area and partition of sectors in the blocks.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 9, 2014
    Inventors: HSIAO-HUA LU, CHIH-MING KUO, YU-CHUN WANG
  • Publication number: 20140008111
    Abstract: A carrier with three-dimensional capacitor includes a substrate and a three-dimensional capacitor, wherein the substrate comprises a trace layer having a first terminal and a second terminal. The three-dimensional capacitor is integrally formed as one piece with the trace layer. The three-dimensional capacitor and the trace layer are made of same material. The three-dimensional capacitor comprises a first capacitance portion and a second capacitance portion, the first capacitance portion comprises a first section, a second section and a first passage, the second capacitance portion is formed at the first passage. The second capacitance portion comprises a third section, a fourth section and a second passage communicated with the first passage. The first capacitance portion is located at the second passage, a first end of the first capacitance portion connects to the first terminal, and a third end of the second capacitance portion connects to the second terminal.
    Type: Application
    Filed: October 4, 2012
    Publication date: January 9, 2014
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chih-Ming Kuo, Lung-Hua Ho, You-Ming Hsu
  • Publication number: 20130334671
    Abstract: A semiconductor package includes a lead frame, at least one chip and a molding compound. The lead frame comprises a plurality of leads, each lead comprises a first end portion and at least one coupling protrusion, wherein the first end portion comprises a first upper surface, the coupling protrusion comprises a ring surface and is integrally formed as one piece with the first upper surface. The chip disposed on top of the leads comprises a plurality of bumps and a plurality of solders, the coupling protrusions embed into the solders to make the ring surfaces of the coupling protrusions cladded with the solders. The solders cover the first upper surfaces. The chip and the leads are cladded with the molding compound.
    Type: Application
    Filed: September 13, 2012
    Publication date: December 19, 2013
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chih-Ming Kuo, Shih-Chieh Chang, Chih-Hsien Ni, Chin-Tang Hsieh, Chia-Jung Tu, Lung-Hua Ho
  • Publication number: 20130334681
    Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.
    Type: Application
    Filed: June 18, 2012
    Publication date: December 19, 2013
    Applicant: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chin-Tang Hsieh, Chih-Ming Kuo, Chia-Jung Tu, Shih-Chieh Chang, Chih-Hsien Ni, Lung-Hua Ho, Chaun-Yu Wu, Kung-An Lin