Patents by Inventor Chih-Ming Lai

Chih-Ming Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LANDING METAL ETCH PROCESS FOR IMPROVED OVERLAY CONTROL
    Publication number: 20200176267
    Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.
    Type: Application
    Filed: November 19, 2019
    Publication date: June 4, 2020
    Inventors: Chih-Min HSIAO, Chih-Ming LAI, Chien-Wen LAI, Ya Hui CHANG, Ru-Gun LIU
  • Spacer etching process for integrated circuit design
    Patent number: 10665467
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee, Jyu-Horng Shieh, Ken-Hsien Hsieh, Ming-Feng Shieh, Shau-Lin Shue, Shih-Ming Chang, Tien-I Bao, Tsai-Sheng Gau
  • Via Connection to a Partially Filled Trench
    Publication number: 20200152476
    Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.
    Type: Application
    Filed: December 17, 2019
    Publication date: May 14, 2020
    Inventors: Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • METAL WITH BURIED POWER FOR INCREASED IC DEVICE DENSITY
    Publication number: 20200134128
    Abstract: A method of designing a layout includes generating first routing tracks assigned to a first color group, generating second routing tracks assigned to a second color group, wherein a first routing track of the first routing tracks is between adjacent second routing tracks of the second routing tracks, and specifying a color stitching region connecting a selected first routing track of the first routing tracks with a selected second routing track of the second routing tracks of the layout, wherein the color stitching region represents a conductive region that connects a first conductive element represented by the selected first routing track with a second conductive element represented by the selected second routing track through an exposed portion of the selected first routing track, and wherein the exposed portion is at a removed portion of a sidewall structure surrounding the selected first routing track.
    Type: Application
    Filed: October 30, 2019
    Publication date: April 30, 2020
    Inventors: Shih-Wei PENG, Chih-Ming LAI, Hui-Ting YANG, Jiann-Tyng TZENG, Wei-Cheng LIN
  • LINE SPACE, ROUTING AND PATTERNING METHODOLOGY
    Publication number: 20200135637
    Abstract: A method of manufacturing a semiconductor device including the operations of defining a first metal pattern (MX-1) having a first metal pattern pitch (MX-1P); depositing an insulating layer over the first metal pattern; defining a core grid having a plurality of core locations having a coreX pitch (CoreXP) on the insulating layer; removing predetermined portions of the insulating layer to form a plurality of core openings through a predetermined set of the core locations; and elongating the core openings using a directional etch (DrE) to form expanded core openings that are used to form the next metal layer MX pattern.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 30, 2020
    Inventors: Shih-Wei PENG, Chih-Ming LAI, Jiann-Tyng TZENG, Wei-Cheng LIN
  • Methods of Forming Metal Layer Structures in Semiconductor Devices
    Publication number: 20200111702
    Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Inventors: Ethan Hsiao, Chien Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen, Ru-Gun Liu
  • SELF ALIGNED LITHO ETCH PROCESS PATTERNING METHOD
    Publication number: 20200105528
    Abstract: A method of defining a pattern-includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.
    Type: Application
    Filed: July 3, 2019
    Publication date: April 2, 2020
    Inventors: Chih-Min HSIAO, Chien Wen LAI, Shih-Chun HUANG, Yung-Sung YEN, Chih-Ming LAI, Ru-Gun LIU
  • CONTACT STRUCTURE, METHOD, LAYOUT, AND SYSTEM
    Publication number: 20200105660
    Abstract: An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.
    Type: Application
    Filed: August 28, 2019
    Publication date: April 2, 2020
    Inventors: Kam-Tou SIO, Cheng-Chi CHUANG, Chih-Ming LAI, Jiann-Tyng TZENG, Wei-Cheng LIN, Lipen YUAN
  • METHOD AND STRUCTURE TO REDUCE CELL WIDTH IN INTEGRATED CIRCUITS
    Publication number: 20200104445
    Abstract: An integrated circuit includes an active zone extending in a first direction, and a spacer extending in a second direction perpendicular to the first direction. The spacer protrudes into a substrate and divides the active zone into a first part and a second part. The integrated circuit includes a first conductive segment and a second conductive segment each extending in the second direction and in a middle layer between the substrate and a metal layer. The first conductive segment forms conductive contact with an active region of a first transistor in the first part of the active zone, and the second conductive segment forms conductive contact with an active region of the second transistor in the second part of the active zone. The spacer joins the first conductive segment and the second conductive segment while electrically isolating the first conductive segment from the second conductive segment.
    Type: Application
    Filed: August 5, 2019
    Publication date: April 2, 2020
    Inventors: Shih-Wei PENG, Chih-Ming LAI, Jiann-Tyng TZENG, Wei-Cheng LIN
  • CAPACITANCE REDUCTION BY METAL CUT DESIGN
    Publication number: 20200098631
    Abstract: The present disclosure describes a method for forming metal interconnects in an integrated circuit (IC). The method includes placing a metal interconnect in a layout area, determining a location of a redundant portion of the metal interconnect, and reducing, at the location, the length of the metal interconnect by a length of the redundant portion to form one or more active portions of the metal interconnect. The length of the redundant portion is a function of a distance between adjacent gate structures of the IC. The method further includes forming the one or more active portions on an interlayer dielectric (ILD) layer of the IC and forming vias on the one or more active portions, wherein the vias are positioned about 3 nm to about 5 nm away from an end of the one or more active portions.
    Type: Application
    Filed: August 5, 2019
    Publication date: March 26, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiung Lin, Yu-Xuan Huang, Chih-Ming Lai, Ru-Gun Liu, Shang-Wen Chang, Yi-Hsun Chiu
  • VIA RAIL SOLUTION FOR HIGH POWER ELECTROMIGRATION
    Publication number: 20200083182
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first conductive interconnect wire extending in a first direction over a substrate. A second conductive interconnect wire is arranged over the first conductive interconnect wire. A via rail is configured to electrically couple the first conductive interconnect wire and the second conductive interconnect wire. The first conductive interconnect wire and the second conductive interconnect wire extend as continuous structures past one or more sides of the via rail.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Kam-Tou Sio, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng, Ru-Gun Liu, Wen-Hao Chen
  • Hybrid Double Patterning Method for Semiconductor Manufacture
    Publication number: 20200083058
    Abstract: A method of fabricating an integrated circuit (IC) uses a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution. The method includes deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution. The method further includes classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Ken-Hsien Hsieh, Wen-Li Cheng, Dong-Yo Jheng, Chih-Ming Lai, Ru-Gun Liu
  • METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE
    Publication number: 20200066523
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming first spacers over inner walls of the trench. The method includes removing a portion of the first spacers. The method includes forming a filling layer into the trench to cover the first spacers. The filling layer and the first spacers together form a strip structure. The method includes removing the first layer. The method includes forming second spacers over two opposite first sidewalls of the strip structure.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Inventors: Chih-Ming LAI, Shih-Ming CHANG, Wei-Liang LIN, Chin-Yuan TSENG, Ru-Gun LIU
  • System for and method of fabricating an integrated circuit
    Patent number: 10565348
    Abstract: A method of fabricating an integrated circuit is disclosed. The method includes defining a via grid, generating a first layout design of the integrated circuit based on at least the via grid or design criteria, generating a standard cell layout design of the integrated circuit, generating a via color layout design of the integrated circuit based on the first layout design and the standard cell layout design, performing a color check on the via color layout design based on design rules, and fabricating the integrated circuit based on at least the via color layout design. The first layout design has a first set of vias arranged in first rows and first columns based on the via grid. The standard cell layout design has standard cells and a second set of vias arranged in the standard cells. The via color layout design has a third set of vias.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: February 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Lin, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shih-Wei Peng, Wei-Chen Chien
  • High-Density Semiconductor Device
    Publication number: 20200043741
    Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.
    Type: Application
    Filed: October 14, 2019
    Publication date: February 6, 2020
    Inventors: Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Hsin-Chih Chen, Shi Ning Ju, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Cheng Lin, Wei-Liang Lin
  • DUMMY MOL REMOVAL FOR PERFORMANCE ENHANCEMENT
    Publication number: 20200020588
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.
    Type: Application
    Filed: September 22, 2019
    Publication date: January 16, 2020
    Inventors: Hui-Ting Yang, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Meng-Hung Shen, Ru-Gun Liu, Wei-Cheng Lin
  • Advanced Metal Connection With Metal Cut
    Publication number: 20200020625
    Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
  • INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20200021292
    Abstract: An integrated circuit includes a first gate, a second gate, a first contact and a first insulating layer. The first gate extends in the first direction and is located on a first level. The second gate extends in the first direction, is located on the first level, and is separated from the first gate in a second direction different from the first direction. The first contact extends in the second direction, overlaps the first gate and the second gate, is located on a second level different from the first level, and is coupled to at least the first gate. The first insulating layer extends in the second direction, overlaps the first gate and the second gate, and is between the second gate and the first contact.
    Type: Application
    Filed: July 9, 2019
    Publication date: January 16, 2020
    Inventors: Shih-Wei PENG, Cheng-Chi CHUANG, Chih-Ming LAI, Jiann-Tyng TZENG, Wei-Cheng LIN
  • PATTERN FORMATION METHOD USING A PHOTO MASK FOR MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20200004137
    Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.
    Type: Application
    Filed: February 27, 2019
    Publication date: January 2, 2020
    Inventors: Ru-Gun LIU, Chin-Hsiang LIN, Cheng-I HUANG, Chih-Ming LAI, Lai Chien WEN, Ken-Hsien HSIEH, Shih-Ming CHANG, Yuan-Te HOU
  • METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES
    Publication number: 20200006078
    Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.
    Type: Application
    Filed: January 4, 2019
    Publication date: January 2, 2020
    Inventors: Ru-Gun LIU, Chih-Ming LAI, Wei-Liang LIN, Yung-Sung YEN, Ken-Hsien HSIEH, Chin-Hsiang LIN